# US 11,309,268 B2 · Method of designing a layout, method of making a semiconductor structure and semiconductor structure

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- Number: US 11,309,268 B2
- Document ID: US11309268B2
- Status: Granted
- Kind: B2
- Application number: 16/904,176
- Filed: 2020-06-17
- Published: 2020-10-08
- Granted: 2022-04-19
- Earliest claimed: 2017-04-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Gulbagh Singh; Chih-Ming Lee; Chi-Yen Lin; Wen-Chang Kuo; C. C. Liu
- Web page: https://patentgrep.com/patent/US11309268B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/48: Insulating materials thereof
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4424: {Copper alloys}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/4446: {Refractory-metal alloys}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/301: {for alignment}
- H10W 46/503: {Located in scribe lines}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/129: {forming a chip-scale package [CSP]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.

## Claims

### Claim 1

A method of designing a layout, the method comprising:
determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads;
generating a second layout pattern;
checking whether an edge of the second layout pattern overlaps the first layout pattern; and
adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein adjusting the second layout pattern comprises extending the edge of the second layout pattern.

### Claim 3 (depends on 1)

The method of claim 1, further comprising extending a contact pad of the plurality of contact pads to overlap with the second layout pattern in response to the determination that the edge of the second layout pattern is separated from the first layout pattern.

### Claim 4 (depends on 3)

The method of claim 3, wherein extending the contact pad comprises extending the contact pad in a plurality of directions.

### Claim 5 (depends on 3)

The method of claim 3, wherein extending the contact pad comprises extending an entire width of the contact pad in a first direction, and width is measured in a second direction perpendicular to the first direction.

### Claim 6 (depends on 3)

The method of claim 3, wherein extending the contact pad comprises extending less than an entire width of the contact pad in a first direction, and width is measured in a second direction perpendicular to the first direction.

### Claim 7 (depends on 3)

The method of claim 3, wherein extending the contact pad comprises extending the contact pad in a first direction at an angle with respect to a first edge of the contact pad, and the angle ranges from about 0 degrees to about 60 degrees.

### Claim 8

A method of making a semiconductor structure comprising:
forming an interconnect structure over a substrate;
forming a first contact pad over a circuit region of the interconnect structure;
forming a second contact pad over a non-circuit region of the interconnect structure; and
depositing a first buffer layer over the first contact pad and second contact pad, wherein an edge of the first buffer layer is over the second contact pad, and the first buffer layer exposes an edge of the second contact pad farthest from the first contact pad.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming an opening in the first buffer layer to expose a portion of the first contact pad.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a post passivation interconnect (PPI) in the opening.

### Claim 11 (depends on 8)

The method of claim 8, further comprising depositing a second buffer layer over the first buffer layer, wherein the second buffer layer covers the edge of the second contact pad farthest from the first contact pad.

### Claim 12 (depends on 11)

The method of claim 11, wherein depositing the second buffer layer comprises at least partially covering a third contact pad, and the second contact pad is between the first contact pad and the third contact pad.

### Claim 13 (depends on 11)

The method of claim 11, wherein depositing the second buffer layer comprises depositing the second buffer layer using a same deposition process as for the first buffer layer.

### Claim 14 (depends on 8)

The method of claim 8, further comprising depositing a second buffer layer over the first buffer layer, wherein the second buffer layer covers more of the second contact pad than the first buffer layer, and the second buffer layer exposes the edge of the second contact pad farthest from the first contact pad.

### Claim 15 (depends on 8)

The method of claim 8, wherein depositing the first buffer layer comprises completely covering a third contact pad, wherein the third contact pad is between the first contact pad and the second contact pad.

### Claim 16

A semiconductor structure comprising:
an interconnect structure;
a first contact pad over a circuit region of the interconnect structure;
a seal ring in the interconnect structure, wherein the seal ring is electrically isolated from the first contact pad;
a second contact pad over the seal ring; and
a first buffer layer over the first contact pad and second contact pad, wherein the first buffer layer is partially over the second contact pad, and an edge of the second contact pad farthest from the first contact pad extends beyond the first buffer layer.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein the second contact pad extends into the circuit region.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, further comprising a post passivation interconnect (PPI) extending through the first buffer layer and electrically connected to the first contact pad.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, wherein the first buffer layer extends over an entirety of a third contact pad, wherein the third contact pad is between the first contact pad and the second contact pad.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, further comprising a second buffer layer over the first buffer layer, wherein the second buffer layer covers an entirety of the second contact pad.