# US 11,309,267 B2 · Semiconductor device including uneven contact in passivation layer and method of manufacturing the same

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- Number: US 11,309,267 B2
- Document ID: US11309267B2
- Status: Granted
- Kind: B2
- Application number: 16/929,109
- Filed: 2020-07-15
- Published: 2022-01-20
- Granted: 2022-04-19
- Earliest claimed: 2020-07-15
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Yen-Jui Chu; Jin-Neng Wu
- Web page: https://patentgrep.com/patent/US11309267B2

## CPC

- H10W 72/075: {of bond wires}
- H10W 72/90: Bond pads, in general
- H10W 72/019: {of bond pads}
- H10W 72/50: Bond wires
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/01923: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01955: {by using masks}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/251: {Materials}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/551: {Materials of bond wires}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a semiconductor device including a substrate, a passivation layer, and a connector. The passivation layer is disposed on the substrate. The connector is embedded in the passivation. An interface of the connector in contact with the passivation layer is uneven, thereby improving the structural stability of the connector. A method of manufacturing the semiconductor is also provided.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a passivation layer on the substrate by a first 3D printing technology, wherein the first 3D printing technology comprises:
ejecting an insulation ink onto the substrate; and
performing a curing step to cure the insulation ink into the passivation layer, wherein after the curing step, the passivation layer forms an opening with an uneven sidewall; and
after forming the passivation layer by the first 3D printing technology, forming a connector in the opening by a second 3D printing technology.

### Claim 2 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, wherein the opening has a body portion and a protrusion portion, the protrusion portion protrudes from the body portion to the passivation layer.

### Claim 3 (depends on 2)

The method of manufacturing the semiconductor device according to claim 2, wherein a ratio of a height of the body portion and a width of the protrusion portion is 10:4 to 10:1.

### Claim 4 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, wherein the forming the connector by the second 3D printing technology comprises using a conductive ink, the conductive ink comprises a plurality of metal nanoparticles, and the plurality of metal nanoparticles comprise silver nanoparticles, copper-silver nanoparticles, copper nanoparticles, or a combination thereof.

### Claim 5 (depends on 4)

The method of manufacturing the semiconductor device according to claim 4, wherein the plurality of metal nanoparticles is in direct contact with the passivation layer.

### Claim 6 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, wherein a material of the passivation layer comprises a hydrophobic material.

### Claim 7 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, further comprising connecting the substrate to a circuit substrate by a wire bonding or a flip-chip bonding, wherein the connector is electrically connected to the substrate and the circuit substrate.

### Claim 8 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, further comprising:
forming a first circuit layer between the substrate and the connector; and
forming a second circuit layer on the connector, wherein the connector is electrically connected to the first and second circuit layers.

### Claim 9 (depends on 1)

The method of manufacturing the semiconductor device according to claim 1, further comprising forming an adhesive layer between the connector and the substrate by an additional 3D printing technology, wherein the adhesive layer comprises a self-assembled monolayer.