# US 11,309,265 B2 · Methods of fabricating semiconductor devices having conductive pad structures with multi-barrier films

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- Number: US 11,309,265 B2
- Document ID: US11309265B2
- Status: Granted
- Kind: B2
- Application number: 16/503,773
- Filed: 2019-07-05
- Published: 2020-01-30
- Granted: 2022-04-19
- Earliest claimed: 2018-07-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Po-Hsun Huang; Po-Han Wang; Ing-Ju Lee; Chao-Lung Chen; Cheng-Ming Wu
- Web page: https://patentgrep.com/patent/US11309265B2

## CPC

- H10W 20/033: {in openings in dielectrics}
- H10W 72/019: {of bond pads}
- H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12}
- H10F 39/8053: {Colour filters}
- H10F 39/8063: {Microlenses}
- H10F 39/811: {Interconnections}
- H10P 14/44: Physical vapour deposition [PVD]
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 72/90: Bond pads, in general
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
forming an interconnect structure on a substrate, wherein the interconnect structure comprises a top metal layer;
forming a first barrier film on the top metal layer using a first deposition process with a first level of power;
forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power;
forming an aluminum-containing layer on the second barrier film; and
patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure,
wherein the first barrier film and the second barrier film are made of metal nitride, and the second barrier film has a nitrogen (N) atomic percentage that is higher than the nitrogen (N) atomic percentage of the first barrier film.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the first level of power is in a range from about 2000 W to about 10000 W.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein the second level of power is in a range from about 100 W to lower than about 2000 W.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein both the first barrier film and the second barrier film are made of tantalum-nitride (TaN).

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein the second barrier film has an atomic ratio of N to TaN that is in a range from about 2.5 times to about 5 times greater than the atomic ratio of N to TaN of the first barrier film.

### Claim 6 (depends on 4)

The method as claimed in claim 4, wherein the first barrier film has an atomic ratio of N to TaN in a range from about 0.19 to about 0.31.

### Claim 7 (depends on 4)

The method as claimed in claim 4, wherein the second barrier film has an atomic ratio of N to TaN in a range from about 0.86 to about 0.93.

### Claim 8 (depends on 1)

The method as claimed in claim 1, wherein the second barrier film has a thickness that is less than the thickness of the first barrier film.

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein the top metal layer is made of copper (Cu), and the aluminum-containing layer is made of aluminum-copper (AlCu) alloy.

### Claim 10

A method of fabricating a semiconductor device, comprising:
forming an interconnect structure over a substrate, wherein the interconnect structure comprises a top metal layer;
forming a passivation layer on the interconnect structure;
forming an opening in the passivation layer to expose the top metal layer;
depositing a first tantalum-nitride (TaN) film in the opening using a first deposition process with a first level of power;
depositing a second tantalum-nitride (TaN) film on the first TaN film using a second deposition process with a second level of power that is lower than the first level of power;
depositing an aluminum-containing layer on the second TaN film; and
patterning the aluminum-containing layer, the second TaN film and the first TaN film to form a conductive pad structure in the opening and in contact with the top metal layer.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the top metal layer is made of copper (Cu), and the aluminum-containing layer is made of an aluminum-copper (AlCu) alloy.

### Claim 12 (depends on 10)

The method as claimed in claim 10, wherein the second TaN film has a nitrogen (N) atomic percentage that is higher than the nitrogen (N) atomic percentage of the first TaN film.

### Claim 13 (depends on 10)

The method as claimed in claim 10, wherein the first level of power is in a range from about 2000 W to about 10000 W.

### Claim 14 (depends on 13)

The method as claimed in claim 13, wherein the second level of power is in a range from about 100 W to lower than about 2000 W.

### Claim 15 (depends on 10)

The method as claimed in claim 10, wherein the first TaN film has a thickness in a range from about 2.5 times to about 70 times greater than a thickness of the second TaN film.

### Claim 16 (depends on 10)

The method as claimed in claim 10, wherein the first TaN film has a first N to TaN atomic ratio, the second TaN film has a second N to TaN atomic ratio, and a ratio of the second N to TaN atomic ratio to the first N to TaN atomic ratio is in a range from about 2.5 to about 5.

### Claim 17

A method of fabricating a semiconductor device, comprising:
forming an interconnect structure over a substrate, wherein the interconnect structure comprises a top metal layer; and
forming a conductive pad structure over the interconnect structure, comprising:
depositing a first barrier film over the top metal layer;
depositing a second barrier film over the first barrier film; and
depositing an aluminum-containing layer over the second barrier film,
wherein the first barrier film is made of a first material having a first nitrogen (N) atomic percentage and the second barrier film is made of a second material having a second nitrogen (N) atomic percentage, and the second barrier film has a higher compressive stress than that of the first barrier film.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein the second barrier film has a thickness that is less than the thickness of the first barrier film.

### Claim 19 (depends on 17)

The method as claimed in claim 17, wherein the second N atomic percentage of the second barrier film is in a range from about 2.5 times to about 5 times greater than the first N atomic percentage of the first barrier film.

### Claim 20 (depends on 17)

The method as claimed in claim 17, wherein the first barrier film is deposited using a first deposition process with a first level of power, and the second barrier film is deposited using a second deposition process with a second level of power that is lower than the first level of power.