# US 11,309,263 B2 · Semiconductor device structure with air gap structure and method for preparing the same

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- Number: US 11,309,263 B2
- Document ID: US11309263B2
- Status: Granted
- Kind: B2
- Application number: 16/871,923
- Filed: 2020-05-11
- Published: 2021-11-11
- Granted: 2022-04-19
- Earliest claimed: 2020-05-11
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Tzu-Ching Tsai
- Web page: https://patentgrep.com/patent/US11309263B2

## CPC

- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/485: {Bit line contacts}
- H10W 20/076: {in via holes or trenches}
- H10W 20/46: comprising air gaps
- H10W 72/00: Interconnections or connectors in packages
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W 20/084: {for dual-damascene structures}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure provides a semiconductor device structure with an air gap structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive contact and a second conductive contact disposed over a semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive contact and the second conductive contact, and a second dielectric layer disposed over the first conductive contact, the second conductive contact and the first dielectric layer. The first dielectric layer is separated from the semiconductor substrate by a first air gap structure, the first dielectric layer is separated from the second dielectric layer by a second air gap structure, and the air gap structures reduce capacitive coupling between conductive features.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a semiconductor substrate having a pattern-dense region and a pattern-loose region;
an isolation member defining a first active area and a second doped region in the pattern-dense region;
a first doped region and a second doped region positioned in the first active area and the second active area;
a first metal plug disposed on the first doped region and a second metal plug disposed on the first doped region in the second active area;
a third metal plug and a fourth metal plug disposed over a pattern-loose region of the semiconductor substrate; and
a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate, wherein a first portion of the dielectric layer between the first metal plug and the second metal plug is separated from the semiconductor substrate by a first air gap, and a second portion of the dielectric layer between the third metal plug and the fourth metal plug is in direct contact with the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein a height of the second portion is greater than a height of the first portion.

### Claim 3 (depends on 1)

The semiconductor device structure of claim 1, wherein the height of the second portion is substantially the same as a height of the third metal plug.

### Claim 4 (depends on 1)

The semiconductor device structure of claim 1, wherein a width of the second portion of the dielectric layer is greater than a width of the first portion of the dielectric layer.

### Claim 5 (depends on 1)

The semiconductor device structure of claim 1, wherein the first air gap is enclosed by a liner layer.

### Claim 6 (depends on 1)

The semiconductor device structure of claim 1, wherein the first metal plug is separated from the second metal plug by a first distance, the third metal plug is separated from the fourth metal plug by a second distance, and the second distance is greater than the first distance.

### Claim 7 (depends on 1)

The semiconductor device structure of claim 1, wherein the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug are covered by the dielectric layer, and a top surface of the first metal plug is higher than a bottom surface of the first portion of the dielectric layer.

### Claim 8 (depends on 1)

The semiconductor device structure of claim 1, further comprising:
a first word line buried in a first trench adjacent to the first doped region;
a high-level bit line contact positioned on the first doped region;
a second air gap surrounding the high-level bit line contact;
wherein the first word line comprises a lower electrode structure and an upper electrode structure on the lower electrode structure;
wherein the upper electrode structure comprises: a source layer substantially covering a sidewall of the first trench; a conductive layer disposed on the source layer; and a work-function adjustment layer disposed between the source layer and the conductive layer.

### Claim 9 (depends on 8)

The semiconductor device structure of claim 8, further comprising:
a second word line buried in a second trench in the second active area of the semiconductor substrate, the second active area being separated from the first active area by the isolation member, and the second doped region being positioned adjacent to the second word line;
a low-level bit line positioned over the second doped region; and
a third second air gap positioned adjacent to the low-level bit line.

### Claim 10 (depends on 9)

The semiconductor device structure of claim 9, further comprising:
a high-level bit line positioned on the high-level bit line contact; and
a low-level bit line contact positioned between the low-level bit line and the second doped region;
wherein a height of the low-level bit line contact is less than a height of the high-level bit line contact.

### Claim 11 (depends on 10)

The semiconductor memory device of claim 10, wherein a width of the low-level bit line is greater than a width of the low-level bit line contact.

### Claim 12 (depends on 10)

The semiconductor memory device of claim 10, wherein a width of the high-level bit line is greater than a width of the high-level bit line contact.

### Claim 13 (depends on 10)

The semiconductor memory device of claim 10, wherein a height of the high-level bit line contact is substantially the same as a combined height of the low-level bit line contact and the low-level bit line.

### Claim 14 (depends on 10)

The semiconductor memory device of claim 10, wherein a top surface of the high-level bit line contact and a top surface of the low-level bit line are substantially at the same level.

### Claim 15 (depends on 10)

The semiconductor memory device of claim 10, wherein the high-level bit line is asymmetrically positioned on the high-level bit line contact.

### Claim 16 (depends on 8)

The semiconductor memory device of claim 8, wherein a work function of the lower electrode structure is higher than a work function of the upper electrode structure.

### Claim 17 (depends on 8)

The semiconductor memory device of claim 8, wherein the work-function adjustment layer conformally covers an inner sidewall of the source layer.

### Claim 18 (depends on 8)

The semiconductor memory device of claim 8, wherein the source layer extends between the lower electrode structure and the conductive layer to cover a top surface of the lower electrode structure.

### Claim 19 (depends on 8)

The semiconductor memory device of claim 8, wherein the work-function adjustment layer includes a metal or a metal nitride, and wherein the work-function adjustment element includes lanthanum (La).

### Claim 20

A method for forming a semiconductor device structure, comprising:
forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate, wherein the first metal plug and the second metal plug are formed over a pattern-dense region of the semiconductor substrate, and the third metal plug and the fourth metal plug are over a pattern-loose region of the semiconductor substrate;
forming an energy removable liner covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug;
performing an etching process to remove a portion of the energy removable layer from the substrate, while remaining an energy removable block between the first metal plug and the second metal plug in the cell region;
forming a dielectric layer covering the energy removable block and the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug;
performing a thermal treating process to transform the energy removable layer into an air gap structure including an air gap enclosed by liner layer;
wherein a first portion of the dielectric layer extends between the first metal plug and the second metal plug such that the first portion of the dielectric layer and the semiconductor substrate are separated by the air gap while a second portion of the dielectric layer extends between the third metal plug and the fourth metal plug such that the second portion of the dielectric layer is in direct contact with the semiconductor substrate.