# US 11,309,262 B2 · Device having physically unclonable function, method for manufacturing same, and chip using same

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- Number: US 11,309,262 B2
- Document ID: US11309262B2
- Status: Granted
- Kind: B2
- Application number: 17/073,844
- Filed: 2020-10-19
- Published: 2021-02-04
- Granted: 2022-04-19
- Earliest claimed: 2017-09-01
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Dong Wang; Xiao Yan Bao; Tian Hua Dong; Guang Ning Li
- Web page: https://patentgrep.com/patent/US11309262B2

## CPC

- H10W 42/405: {using active circuits}
- G06F 21/72: in cryptographic circuits
- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- H04L 9/3278: {using physically unclonable functions [PUF]}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10P 32/171: {being group IV material}
- H10P 32/302: {Doping polycrystalline silicon or amorphous silicon layers}
- G06F 2221/2107: File encryption
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same. The may method include: providing a substrate structure that comprises: a substrate comprising encryption device areas and reference device areas; at least one first gate structure on the encryption device areas and used in an encryption device and a first spacer layer on a side wall of the first gate structure; a first interconnection layer on the encryption device areas and the first spacer layer; at least one second gate structure on the reference device areas and used in a reference device and a second spacer layer on a side wall of the second gate structure; and a second interconnection layer on the reference device area and the second spacer layer; performing first ion injection, so as to introduce first impurities into the first interconnection layer; performing second ion injection, so as to introduce second impurities into the first and second interconnection layers, where a password of the device having a physically unclonable function is determined according to a drain current of each encryption device and a drain current of a reference device corresponding to the encryption device.

## Claims

### Claim 1

A device having a physically unclonable function, comprising:
a substrate comprising encryption device areas and reference device areas;
an encryption device array comprising at least one encryption device, where each encryption device comprises:
a first gate structure on the encryption device areas;
a first spacer layer on a side wall of the first gate structure;
a first interconnection layer on the encryption device areas and the first spacer layer; and
a first source area and a first drain area in the encryption device areas at two sides of the first gate structure; and
a reference device array comprising at least one reference device, where each reference device comprises:
a second gate structure on the reference device areas;
a second spacer layer on a side wall of the second gate structure;
a second interconnection layer on the reference device areas and the second spacer layer; and
a second source area and a second drain area in the reference device areas at two sides of the second gate structure,
wherein the first interconnection layer comprises first impurities comprising a Group IV element and does not comprise second impurities comprising a Group V element and the second interconnection layer comprises both the first impurities and the second impurities.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the password of the device having a physically unclonable function is determined according to a difference between the drain current of each encryption device and the drain current of the reference device corresponding to the encryption device.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the first gate of the first gate structure comprises the first impurities introduced through first ion injection.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the first impurities comprise one or more selected from a group consisting of: Ge, Si, and C.

### Claim 5 (depends on 1)

The device according to claim 1, wherein:
a top of the first spacer layer is higher than a top of the first gate of the first gate structure; and
a top of the second spacer layer is higher than a top of the second gate of the second gate structure.

### Claim 6 (depends on 1)

The device according to claim 1, wherein:
materials of the first interconnection layer and the second interconnection layer comprise polysilicon.

### Claim 7 (depends on 1)

The device according to claim 1, wherein one encryption device corresponds to one reference device.

### Claim 8 (depends on 1)

The device according to claim 1, wherein a plurality of encryption devices corresponds to one reference device.

### Claim 9 (depends on 1)

A chip, comprising a device having a physically unclonable function according to claim 1.
