# US 11,309,258 B2 · Semiconductor structure

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- Number: US 11,309,258 B2
- Document ID: US11309258B2
- Status: Granted
- Kind: B2
- Application number: 16/921,850
- Filed: 2020-07-06
- Published: 2020-12-24
- Granted: 2022-04-19
- Earliest claimed: 2019-06-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Tung-Jiun Wu; Yinlung Lu; Mingni Chang; Ming-Yih Wang
- Web page: https://patentgrep.com/patent/US11309258B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10D 1/692: {Electrodes}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.

## Claims

### Claim 1

A semiconductor structure comprising:
a substrate;
a MIM capacitor disposed over the substrate;
a first insulating layer disposed over the MIM capacitor;
an oxide-nitride-oxide-nitride (ONON) stack disposed over the first insulating layer;
a connecting via disposed in the first insulating layer; and
a connecting pad disposed in the ONON stack and in contact with the connecting via,
wherein the ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad, the ONON stack comprises a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer, and a thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first silicon oxide layer is in contact with the first insulating layer and the portion of the top surface of the connecting pad.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein a thickness of the first silicon oxide layer over the first insulating layer and a thickness of the first silicon oxide layer over the portion of the top surface of the connecting pad are the same.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a second insulating layer; and
a connecting layer disposed in the second insulating layer,
wherein the first insulating layer and the MIM capacitor are disposed over the second insulating layer and the second connecting layer.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the connecting via penetrates a portion of the first insulating layer and a portion of the second insulating layer, and the connecting via is electrically connected to the connecting layer.

### Claim 6 (depends on 4)

The semiconductor structure of claim 4, wherein the MIM capacitor is electrically connected to the connecting layer by the connecting via.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a polymer layer disposed over the ONON stack; and
an external conductor over the polymer layer and electrically connected to the connecting pad,
wherein the polymer layer covers another portion of the top surface of the connecting pad.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the external conductor penetrates the ONON stack.

### Claim 9

A semiconductor structure comprising:
a first insulating layer;
a connecting layer disposed in the first insulating layer;
a MIM capacitor disposed over the first insulating layer and the connecting layer;
a second insulating layer disposed over the MIM capacitor, the first insulating layer and the connecting layer;
an oxide-nitride-oxide-nitride (ONON) stack disposed over the second insulating layer;
a connecting via disposed in the second insulating layer; and
a connecting pad disposed in the ONON stack and in contact with the connecting via,
wherein the ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad, and the MIM capacitor is electrically connected to the connecting layer by the connecting via.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the ONON stack comprises a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the second insulating layer.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the first silicon oxide layer is in contact with the second insulating layer and the portion of the top surface of the connecting pad.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein a thickness of the first silicon oxide layer over the second insulating layer and a thickness of the first silicon oxide layer over the portion of the top surface of the connecting pad are the same.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10, wherein a thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.

### Claim 14 (depends on 9)

The semiconductor structure of claim 9, wherein the connecting via penetrates a portion of the first insulating layer and a portion of the second insulating layer, and the connecting via is electrically connected to the connecting layer.

### Claim 15 (depends on 9)

The semiconductor structure of claim 9, further comprising:
a polymer layer disposed over the ONON stack; and
an external conductor over the polymer layer and electrically connected to the connecting pad,
wherein the polymer layer covers another portion of the top surface of the connecting pad, and the external conductor penetrates the ONON stack.

### Claim 16

A semiconductor structure comprising:
a substrate;
a MIM capacitor disposed over the substrate;
an insulating layer disposed over the MIM capacitor;
an ONON stack disposed over the insulating layer;
a connecting via disposed in the insulating layer;
a connecting pad disposed in the ONON stack and in contact with the connecting via;
a polymer layer disposed over the ONON stack and exposing a portion of the connecting pad;
an external conductor disposed over the connecting pad; and
an under bump metallization disposed on the polymer layer and the portion of the connecting pad exposed through the polymer layer.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein the ONON stack comprises a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the insulating layer.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein the first silicon oxide layer is in contact with the insulating layer and a portion of a top surface of the connecting pad, and a thickness of the first silicon oxide layer over the insulating layer and a thickness of the first silicon oxide layer over the portion of the top surface of the connecting pad are the same.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, wherein the ONON stack covers sidewalls and a portion of a top surface of the connecting pad and the polymer layer covers another portion of the top surface of the connecting pad.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, wherein the external connector and the under bump metallization penetrate the ONON stack.