# US 11,309,256 B2 · Manufacturing method of a semiconductor memory device

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- Number: US 11,309,256 B2
- Document ID: US11309256B2
- Status: Granted
- Kind: B2
- Application number: 16/663,119
- Filed: 2019-10-24
- Published: 2020-11-05
- Granted: 2022-04-19
- Earliest claimed: 2019-05-02
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Kun Young Lee; Tae Kyung Kim
- Web page: https://patentgrep.com/patent/US11309256B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 1/692: {Electrodes}
- H10P 72/00: Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/01: {Manufacture or treatment}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W 72/072: {of bump connectors}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/07254: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/251: {Materials}
- H10W 72/287: {Flow barriers}
- H10W 72/925: {Bond pads having a filler embedded in a matrix}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 80/163: {using active alignment, e.g. detecting marks and correcting position}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory device, the method comprising:
processing a first substrate, wherein processing the first substrate comprises:
disposing a peripheral circuit and a first conductive contact pattern coupled to the peripheral circuit over a first region of the first substrate;
embedding a sacrificial material in a second region of the first substrate; and
disposing a first align mark over the sacrificial material;
processing a second substrate, wherein processing the second substrate comprises disposing a second align mark, a memory cell array, and a second conductive contact pattern coupled to the memory cell array over the second substrate;
orientating the first substrate and the second substrate such that the first conductive contact pattern and the second conductive contact pattern face each other; and
coupling the first conductive contact pattern to the second conductive contact pattern by checking alignment of the first align mark with the second align mark.

### Claim 2 (depends on 1)

The method of claim 1, wherein processing the first substrate comprises:
forming the peripheral circuit at a first surface of the first substrate;
forming a first insulating structure on the first surface of the first substrate to cover the peripheral circuit;
etching the first insulating structure and the second region of the first substrate to form a first groove in the second region of the first substrate;
filling the first groove with the sacrificial material;
forming the first conductive contact pattern coupled to the peripheral circuit and the first align mark disposed over the sacrificial material; and
removing a part of the first substrate from a rear surface of the first substrate opposite the first surface of the first substrate to expose the sacrificial material.

### Claim 3 (depends on 2)

The method of claim 2, further comprising, removing the sacrificial material exposed by removing the part of the first substrate,
wherein checking the alignment of the first align mark with the second align mark comprises checking the alignment through a region from which the sacrificial material was removed.

### Claim 4 (depends on 2)

The method of claim 2, wherein forming the first conductive contact pattern coupled to the peripheral circuit and the first align mark disposed over the sacrificial material comprises:
forming a second insulating structure on the first insulating structure;
forming the first conductive contact pattern coupled to the peripheral circuit and the first align mark contacting the sacrificial material in the second insulating structure;
etching a first part of the second insulating structure to expose an end portion of the first align mark;
removing the end portion of the first align mark such that the first align mark has a shorter length than the first conductive contact pattern; and
etching a second part of the second insulating structure to expose an end portion of the first conductive contact pattern.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming an upper insulating layer over the second substrate, wherein the upper insulating layer has a second groove that exposes the second conductive contact pattern; and
filling the second groove with a conductive adhesive material,
wherein the coupling of the first conductive contact pattern to the second conductive contact pattern comprises:
aligning the end portion of the first conductive contact pattern in the second groove; and
forming a conductive adhesive pattern coupling the first conductive contact pattern to the second conductive contact pattern by heat-curing the conductive adhesive material.

### Claim 6 (depends on 1)

The method of claim 1, wherein processing the second substrate comprises:
forming the memory cell array over the second substrate, wherein the memory cell array includes channel structures that pass through alternately stacked interlayer insulating layers and conductive patterns and includes memory layers that are disposed between the channel structures and the conductive patterns;
forming an insulating structure over the second substrate to cover the memory cell array; and
forming the second conductive contact pattern coupled to the memory cell array, and forming the second align mark over the insulating structure.