# US 11,309,255 B2 · Very thin embedded trace substrate-system in package (SIP) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,255 B2 - Document ID: US11309255B2 - Status: Granted - Kind: B2 - Application number: 16/830,689 - Filed: 2020-03-26 - Published: 2020-07-16 - Granted: 2022-04-19 - Earliest claimed: 2017-09-28 - Assignees: Dialog Semiconductor (UK) Limited - Applicants: Dialog Semiconductor (UK) Limited - Inventors: Jesus Mennen Belonio, Jr.; Shou Cheng Eric Hu; Ian Kent; Ernesto Gutierrez, III; Melvin Martin; Rajesh Subraya Aiyandra - Web page: https://patentgrep.com/patent/US11309255B2 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/016: {using moulds} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 72/00: Interconnections or connectors in packages - H10W 72/07236: {Soldering or alloying} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output. ## Claims ### Claim 1 A method to fabricate a system in package comprising: providing at least one silicon die having a top side and a bottom side wherein a plurality of copper pillars on said top side connect to a circuit layer within said silicon die; providing a substrate comprising: an inner pre-impregnated material layer; at least three metal redistribution layers within said impregnated material; and a solder mask material on top and bottom of said pre-impregnated material; mounting said at least one silicon die in an opening to said metal redistribution layers on a first side of said substrate wherein said plurality of copper pillars electrically contact said metal redistribution layers; embedding said at least one silicon die in a first molding compound; mounting at least one passive component in an opening to said metal redistribution layers on a second side of said substrate opposite to said first side wherein said at least one passive component electrically contacts said metal redistribution layers; embedding said at least one passive component in a second molding compound wherein electrical connections are made between said at least one silicon die and said at least one passive component through said metal redistribution layers; grinding said first molding compound until said bottom side of said at least one silicon die is exposed; thereafter opening vias through said first molding compound to solder pads electrically contacting said metal redistribution layers; and mounting solder balls on said solder pads wherein said solder balls provide package output. ### Claim 2 (depends on 1) The method according to claim 1 wherein said metal redistribution layers comprise copper. ### Claim 3 (depends on 1) The method according to claim 1 wherein there are three said metal redistribution layers. ### Claim 4 (depends on 1) The method according to claim 1 wherein said system in package has a total thickness of between about 700 and 1500 μm. ### Claim 5 (depends on 1) The method according to claim 1 wherein said first and second molding compound comprises an epoxy resin. ### Claim 6 (depends on 1) The method according to claim 1 wherein said substrate is an embedded trace substrate. ### Claim 7 (depends on 1) The method according to claim 1 wherein said substrate is a coreless substrate. ### Claim 8 A method to fabricate a system in package comprising: providing at least one silicon die having a top side and a bottom side wherein a plurality of copper pillars on said top side connect to a circuit layer within said silicon die; providing a substrate having metal redistribution layers therein; mounting said at least one silicon die in an opening to said metal redistribution layers on a first side of said substrate wherein said plurality of copper pillars electrically contact said metal redistribution layers; embedding said at least one silicon die in a first molding compound; mounting at least one passive component in an opening to said metal redistribution layers on a second side of said substrate opposite to said first side wherein said at least one passive component electrically contacts said metal redistribution layers; embedding said at least one passive component in a second molding compound; grinding said first molding compound until said bottom side of said at least one silicon die is exposed; thereafter opening vias through said first molding compound to solder pads electrically contacting said metal redistribution layers; and mounting solder balls on said solder pads wherein said solder balls provide package output. ### Claim 9 (depends on 8) The method according to claim 8 wherein said metal redistribution layers comprise copper. ### Claim 10 (depends on 8) The method according to claim 8 wherein there are three said metal redistribution layers. ### Claim 11 (depends on 8) The method according to claim 8 wherein said system in package has a total thickness of between about 700 and 1500 μm. ### Claim 12 (depends on 8) The method according to claim 8 wherein said first and second molding compound comprises an epoxy resin. ### Claim 13 (depends on 8) The method according to claim 8 wherein said substrate is an embedded trace substrate. ### Claim 14 (depends on 8) The method according to claim 8 wherein said substrate is a coreless substrate.