# US 11,309,254 B2 · Semiconductor device having through silicon vias and method of manufacturing the same

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- Number: US 11,309,254 B2
- Document ID: US11309254B2
- Status: Granted
- Kind: B2
- Application number: 16/793,069
- Filed: 2020-02-18
- Published: 2021-08-19
- Granted: 2022-04-19
- Earliest claimed: 2020-02-18
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Shing-Yih Shih
- Web page: https://patentgrep.com/patent/US11309254B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01257: {by reflowing}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
creating at least one trench in a semiconductor wafer;
depositing an isolation film in the trench;
depositing a conductive material on the isolation film to form at least one conductive line in the trench;
forming a conductive feature, electrically coupled to the conductive line, over a front surface of the semiconductor wafer;
thinning the semiconductor wafer until a back surface of the semiconductor wafer, opposite to the front surface, is below an end surface of the isolation film;
forming a metallic layer over the back surface of the semiconductor wafer and over a portion of a periphery of the isolation film exposed through the semiconductor wafer;
performing a grinding process to remove portions of the metallic layer and the isolation film until the conductive line is exposed; and
forming at least one bump to connect the remaining portions of the metallic layer to the conductive line.

### Claim 2 (depends on 1)

The method of claim 1, further comprising performing a patterning process to remove portions of the metallic layer prior to the formation of the bump.

### Claim 3 (depends on 1)

The method of claim 1, wherein the metallic layer has a topology following the topology of the exposed portions of the isolation film and the back surface of the semiconductor wafer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the metallic layer has a thickness in a range between 1 μm and 5 μm.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
depositing a first dielectric layer on the back surface of the semiconductor wafer and on the portion of the periphery of the isolation film exposed through the semiconductor wafer prior to the formation of the metallic layer; and
removing portions of the first dielectric layer above an end surface of the conductive line during the grinding process,
wherein the first dielectric layer has a substantially uniform thickness.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first dielectric layer has a thickness in a range between 0.5 μm and 3 μm.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
depositing a second dielectric layer on the metallic layer until a top surface of the second dielectric layer, over the semiconductor wafer, is above an end surface of the conductive line; and
removing portions of the second dielectric layer above the end surface of the conductive line during the grinding process,
wherein the second dielectric layer has a substantially uniform thickness.

### Claim 8 (depends on 7)

The method of claim 7, wherein a thickness of the second dielectric layer is in a range between 0.5 μm and 5 μm.

### Claim 9 (depends on 7)

The method of claim 7, further comprising performing a patterning process to sequentially remove portions of the second dielectric layer and the metallic layer.

### Claim 10 (depends on 1)

The method of claim 1, wherein a distance between the end surfaces of the isolation liners and the back surface of the semiconductor wafer is in the range between 0.5 μm and 10 μm.

### Claim 11 (depends on 1)

The method of claim 1, further comprising forming an insulating layer to encase a periphery of the isolation film and the conductive feature concurrent with the formation of the conductive feature.

### Claim 12 (depends on 1)

The method of claim 1, wherein the formation of the trench comprises:
sequentially forming a buffer layer and a sacrificial layer on the front surface of the semiconductor wafer;
forming at least one opening penetrating through the buffer layer and the sacrificial layer; and
etching the semiconductor wafer through the opening to form the trench,
wherein the buffer layer and the sacrificial layer are removed after the deposition of the conductive material, so that an end surface of the conductive line is above the front surface of the semiconductor wafer.

### Claim 13 (depends on 1)

The method of claim 1, wherein the thinning of the semiconductor wafer comprises:
performing a grinding process to reduce a thickness of the semiconductor wafer, wherein the isolation film is not exposed after the performing of the grinding process; and
performing an etching process to further reduce the thickness of the semiconductor wafer until the back surface of the semiconductor wafer is below the end surface of the isolation film.