# US 11,309,253 B2 · Package structure and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,253 B2 - Document ID: US11309253B2 - Status: Granted - Kind: B2 - Application number: 16/858,269 - Filed: 2020-04-24 - Published: 2021-10-28 - Granted: 2022-04-19 - Earliest claimed: 2020-04-24 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Chin-Li Kao - Web page: https://patentgrep.com/patent/US11309253B2 ## CPC - H10W 70/611: {for connecting multiple chips together} - H10P 72/74: {using temporarily an auxiliary support} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/014: {using batch processing} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 72/0198: {batch processes} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A package structure and a method for manufacturing a package structure are provided. The package structure includes a first conductive structure and a second conductive structure. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure is bonded to the first conductive structure. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. A distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure. A size of the second conductive structure is less than a size of the first conductive structure. ## Claims ### Claim 1 A package structure, comprising: a first conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; and a second conductive structure bonded to the first conductive structure, the second conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; wherein a distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure, and a size of the second conductive structure is less than a size of the first conductive structure; and wherein the first conductive structure comprises an inner via, the inner via has a first opening and a second opening opposite to the first opening, the second conductive structure is closer to the first opening than to the second opening, and a width of the first opening is greater than a width of the second opening. ### Claim 2 (depends on 1) The package structure as claimed in claim 1, wherein a gap between a lateral peripheral surface of the second conductive structure and a lateral peripheral surface of the first conductive structure is equal to or less than 75 μm. ### Claim 3 (depends on 1) The package structure as claimed in claim 1, further comprising: at least one conductive connecting element disposed between the second conductive structure and the first conductive structure and bonding the second conductive structure and the first conductive structure together. ### Claim 4 (depends on 1) The package structure as claimed in claim 1, further comprising: a protection layer disposed between the first conductive structure and the second conductive structure, wherein the protection layer includes a portion contacting a first lateral peripheral surface of the second conductive structure. ### Claim 5 (depends on 1) The package structure as claimed in claim 1, further comprising: at least one semiconductor device electrically connected to the first conductive structure, wherein the at least one semiconductor device is closer to the first conductive structure than the second conductive structure is. ### Claim 6 (depends on 4) The package structure as claimed in claim 4, further comprising: an encapsulant encapsulating at least one semiconductor device electrically connected to the first conductive structure, wherein a lateral peripheral surface of the portion of the protection layer is substantially coplanar with a lateral peripheral surface of the encapsulant. ### Claim 7 A package structure, comprising: a first conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; a second conductive structure bonded to the first conductive structure, the second conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer, wherein a distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure; a protection layer between the first conductive structure and the second conductive structure, wherein a portion of the protection layer contacts a lateral peripheral surface of the second conductive structure and has a width increasing along a direction towards the first conductive structure; and a semiconductor device electrically connected to the first conductive structure, wherein the semiconductor device is closer to the first conductive structure than the second conductive structure is. ### Claim 8 (depends on 7) The package structure as claimed in claim 7, wherein the portion of the protection layer directly contacts the lateral peripheral surface of the second conductive structure at an interface, and a ratio of a length of the interface to a length of the lateral peripheral surface of the second conductive structure is greater than 0.8. ### Claim 9 (depends on 7) The package structure as claimed in claim 7, wherein the second conductive structure has a first surface facing the first conductive structure and a second surface opposite to the first surface, and the portion of the protection layer partially covers the second surface of the second conductive structure. ### Claim 10 (depends on 7) The package structure as claimed in claim 7, wherein the second conductive structure has a first surface facing the first conductive structure and a second surface opposite to the first surface, the second conductive structure further includes a solder mask adjacent to the second surface of the second conductive structure, and the portion of the protection layer directly contacts the solder mask. ### Claim 11 (depends on 10) The package structure as claimed in claim 10, wherein the solder mask is recessed from the lateral peripheral surface of the second conductive structure. ### Claim 12 A method for manufacturing a package structure, comprising: (a) forming a first conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer, wherein the first conductive structure further includes at least one unit; (b) forming at least one second conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer, wherein a distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure, and a size of the second conductive structure is less than a size of the unit of the first conductive structure; (c) bonding the at least one second conductive structure to the unit of the first conductive structure; and (e) electrically connecting at least one semiconductor device to the first conductive structure, wherein the at least one semiconductor device is closer to the first conductive structure than the second conductive structure is. ### Claim 13 (depends on 12) The method as claimed in claim 12, wherein after (c), the method further comprises: (d) forming a protection layer between the first conductive structure and the second conductive structure, wherein a portion of the protection layer extends along a lateral peripheral surface of the second conductive structure. ### Claim 14 (depends on 12) The method as claimed in claim 12, wherein after (a), the method further comprises: (a1) conducting a functional testing step to the first conductive structure; and after (b), the method further comprises: (b1) conducting a functional testing step to the second conductive structure. ### Claim 15 (depends on 4) The package structure as claimed in claim 4, wherein the portion of the protection layer has a width increasing along a direction towards the first conductive structure. ### Claim 16 (depends on 5) The package structure as claimed in claim 5, wherein an active surface of the at least one semiconductor device is facing the first conductive structure. ### Claim 17 (depends on 16) The package structure as claimed in claim 16, further comprising: an underfill between the at least one semiconductor device and the first conductive structure. ### Claim 18 (depends on 5) The package structure as claimed in claim 5, further comprising: an encapsulant encapsulating the at least one semiconductor device, wherein a lateral peripheral surface of the encapsulant is substantially coplanar with a lateral peripheral surface of the first conductive structure. ### Claim 19 (depends on 5) The package structure as claimed in claim 5, further comprising an electronic device in the second conductive structure and electrically connected to the at least one semiconductor device. ### Claim 20 (depends on 1) The package structure as claimed in claim 1, wherein a thickness of the first conductive structure is less than a thickness of the second conductive structure. ### Claim 21 (depends on 7) The package structure as claimed in claim 7, wherein an active surface of the semiconductor device is facing the first conductive structure. ### Claim 22 (depends on 21) The package structure as claimed in claim 21, further comprising: an underfill between the semiconductor device and the first conductive structure. ### Claim 23 (depends on 7) The package structure as claimed in claim 7, further comprising: an encapsulant encapsulating the semiconductor device, wherein a lateral peripheral surface of the encapsulant is substantially coplanar with a lateral peripheral surface of the first conductive structure. ### Claim 24 (depends on 7) The package structure as claimed in claim 7, further comprising an electronic device in the second conductive structure and electrically connected to the semiconductor device.