# US 11,309,249 B2 · Semiconductor package with air gap and manufacturing method thereof

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- Number: US 11,309,249 B2
- Document ID: US11309249B2
- Status: Granted
- Kind: B2
- Application number: 16/865,909
- Filed: 2020-05-04
- Published: 2021-11-04
- Granted: 2022-04-19
- Earliest claimed: 2020-05-04
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Tse-Yao Huang
- Web page: https://patentgrep.com/patent/US11309249B2

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 90/00: Package configurations
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/072: {of bump connectors}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 80/011: {Manufacture or treatment of pads or other interconnections to be direct bonded}
- H10W 80/031: {Changing or setting shapes of the pads}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions to of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

## Claims

### Claim 1

A semiconductor package, comprising:
a first semiconductor structure, having a first surface and a first recess recessed from the first surface, and comprising first conductive structures protruding from a bottom surface of the first recess; and
a second semiconductor structure, having a second surface and second recesses recessed from the second surface, and comprising second conductive structures protruding from the second surface, wherein the second semiconductor structure is bonded onto the first semiconductor structure, top surfaces of the first conductive structures are in contact with the second recesses, top surfaces of the second conductive structures are in contact with the bottom surface of the first recess, a portion of the second surface is in contact with the first surface to seal the first recess, so as to form an air gap in the semiconductor package.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein the first conductive structures are laterally surrounded by the air gap.

### Claim 3 (depends on 1)

The semiconductor package according to claim 1, wherein the first semiconductor structure further comprises a stack of first insulating layers and an insulating pattern on the stack of first insulating layers, the first surface is a top surface of the insulating pattern, an inner sidewall of the insulating pattern is a sidewall of the first recess, and the bottom surface of the first recess is a top surface of the stack of first insulating layers.

### Claim 4 (depends on 3)

The semiconductor package according to claim 3, wherein the air gap has a height substantially equal to a thickness of the insulating pattern.

### Claim 5 (depends on 3)

The semiconductor package according to claim 3, wherein the second semiconductor structure further comprises a stack of second insulating layers, the second surface is a surface of the stack of second insulating layers, and the second recess extend through the stack of second insulating layers.

### Claim 6 (depends on 5)

The semiconductor package according to claim 5, wherein a first thickness by which the first conductive structures protrude from the top surface of the stack of first insulating layers substantially equal to a total thickness of the insulating pattern and the stack of second insulating layers.

### Claim 7 (depends on 5)

The semiconductor package according to claim 5, wherein a second thickness by which the second conductive structures protrude from the stack of second insulating layers substantially equal to a thickness of the insulating pattern.

### Claim 8 (depends on 1)

The semiconductor package according to claim 1, wherein the first conductive structures are taller than the second conductive structures, and the second conductive structures are surrounding the first conductive structures.

### Claim 9

A semiconductor package, comprising:
a first semiconductor structure, having a first bonding surface and first protruding portions protruding from the first bonding surface; and
a second semiconductor structure, having a second bonding surface and second protruding portions protruding from the second bonding surface, and bonded to the first semiconductor structure, wherein the first bonding surface is partially in contact with the second bonding surface, a portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package;
wherein the first protruding portions are laterally surrounded by the air gap, the first protruding portions are taller than the second protruding portions, and the second protruding portions are surrounding the first protruding portions, wherein top surfaces of the first protruding portions are in contact with the second bonding surface of the second semiconductor structure.

### Claim 10 (depends on 9)

The semiconductor package according to claim 9 wherein the first bonding surface has a recess portion and the first protruding portions are located within a range of the recess portion.

### Claim 11 (depends on 10)

The semiconductor package according to claim 10, wherein the second protruding portions are in contact with the recess portion of the first bonding surface.

### Claim 12 (depends on 9)

The semiconductor package according to claim 9, wherein the first protruding portions are conductive plugs electrically connecting a first interconnection of the first semiconductor structure and a second interconnection of the second semiconductor structure.

### Claim 13 (depends on 12)

The semiconductor package according to claim 12, wherein the second protruding portions are conductive plugs contacting the second interconnection of the second semiconductor structure and separated from the first interconnection of the first semiconductor structure.