# US 11,309,247 B2 · Semiconductor device, and associated method and system

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- Number: US 11,309,247 B2
- Document ID: US11309247B2
- Status: Granted
- Kind: B2
- Application number: 16/849,985
- Filed: 2020-04-15
- Published: 2021-05-06
- Granted: 2022-04-19
- Earliest claimed: 2019-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Shih-Wei Peng; Wei-Cheng Lin; Jiann-Tyng Tzeng
- Web page: https://patentgrep.com/patent/US11309247B2

## CPC

- H10W 20/0698: {Local interconnections}
- H10W 20/427: {Power or ground buses}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D 84/0158: {the components including FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device, including: a substrate, a transistor layer, a dielectric layer, and a power grid structure. The transistor layer is formed on a first side of the substrate and includes a plurality of active regions for forming transistors. The dielectric layer is formed on the transistor layer and includes a conductive strip disposed on a first active region and extending toward a second active region for signal connection. The power grid structure is formed on a second side of the substrate opposite to the first side and arranged to direct a power source to the transistor layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a transistor layer, on a first side of the substrate, including a first active region configured to be a source/drain terminal of a first transistor and a second active region configured to be a source/drain terminal of a second transistor;
a dielectric layer, a bottom surface of the dielectric layer in direct contact with top surfaces of the source/drain terminals of the first and second transistors, wherein a conductive strip is provided within the dielectric layer and disposed on the first active region and extending toward the second active region for signal connection; and
a power grid structure, on a second side of the substrate opposite to the first side, arranged to direct a power source to the transistor layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the transistor layer includes a first cell including the first active region and the second active region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the conductive strip is connected between the first active region and the second active region for signal connection.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, further comprising:
a plurality of metal strips, on the dielectric layer, extending in a first direction for signal connection,
wherein the conductive strip extends in a second direction orthogonal to the first direction, and one end of the conductive strip is connected to one of the plurality of metal strips for signal connection via a contact via.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the transistor layer includes a first cell and a second cell, the first cell includes the first active region while the second cell includes the second active region, and the conductive strip extends across a boundary between the first cell and the second cell.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the conductive strip is connected between the first active region and the second active region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the conductive strip route through a turning corner.

### Claim 8 (depends on 5)

The semiconductor device of claim 5, further comprising:
a plurality of metal strips, disposed above the dielectric layer, and extends in a first direction for signal connection,
wherein one end of the conductive strip is connected to one of the plurality of metal strips for signal connection via a contact via.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the conductive strip routes through a turning corner.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the conductive strip is isolated from the first active region by an isolation layer.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a transistor layer on a first side of the substrate, the transistor layer including a plurality of active regions for forming transistors;
forming a conductive strip, on a first active region, extending toward to a second active region for signal connection;
forming a dielectric layer on the transistor layer, covering the connecting strip; and forming a power grid structure on a second side of the substrate opposite to the first side, the power grid structure arranged to direct a power source to the transistor layer;
wherein forming the transistor layer on the first side of the substrate comprises:
forming a first cell including the first active region; and
forming a second cell including the second active region;
and forming the conductive strip, on the first active region comprises:
forming the conductive strip extending across a boundary between the first cell and the second cell.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the conductive strip, on the first active region further comprises:
forming the conductive strip connected between the first active region and the second active region.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the conductive strip, on the first active region further comprises:
forming the conductive strip routing through a turning corner.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
forming a plurality of metal strips on the dielectric layer, wherein the plurality of metal strips extends in a first direction for signal connection;
and forming the conductive strip, on the first active region comprises:
forming the conductive strip whose one end is connected to one of the plurality of metal strips for signal connection via a contact via.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the conductive strip, on the first active region comprises:
forming the conductive strip routing through a turning corner.

### Claim 16

A system, comprising:
a storage device, arranged to store a program code; and
a processor, when executed and loaded by the processor, the program code instructs the processor to execute following operations:
providing a substrate;
forming a transistor layer on a first side of the substrate, the transistor layer including a plurality of active regions for forming transistors;
forming a conductive strip, on a first active region, extending toward to a second active region for signal connection;
forming a dielectric layer on the transistor layer, covering the connecting strip; and forming a power grid structure on a second side of the substrate opposite to the first side, the power grid structure arranged to direct a power source to the transistor layer;
wherein forming the transistor layer on the first side of the substrate comprises:
forming a first cell including the first active region; and
forming a second cell including the second active region;
and forming the conductive strip, on the first active region comprises:
forming the conductive strip extending across a boundary between the first cell and the second cell.

### Claim 17 (depends on 16)

The system of claim 16, wherein forming the conductive strip, on the first active region further comprises:
forming the conductive strip connected between the first active region and the second active region.

### Claim 18 (depends on 17)

The system of claim 17, wherein forming the conductive strip, on the first active region further comprises:
forming the conductive strip routing through a turning corner.

### Claim 19 (depends on 16)

The system of claim 16, wherein the program code further instructs the processor to execute following operations:
forming a plurality of metal strips on the dielectric layer, wherein the plurality of metal strips extends in a first direction for signal connection;
and forming the conductive strip, on the first active region comprises:
forming the conductive strip whose one end is connected to one of the plurality of metal strips for signal connection via a contact via.

### Claim 20 (depends on 19)

The system of claim 19, wherein forming the conductive strip, on the first active region comprises:
forming the conductive strip routing through a turning corner.