# US 11,309,246 B2 · High density 3D interconnect configuration

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- Number: US 11,309,246 B2
- Document ID: US11309246B2
- Status: Granted
- Kind: B2
- Application number: 16/783,132
- Filed: 2020-02-05
- Published: 2021-08-05
- Granted: 2022-04-19
- Earliest claimed: 2020-02-05
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Sanjay Dabral; Zhitao Cao; Kunzhong Hu; Jun Zhai
- Web page: https://patentgrep.com/patent/US11309246B2

## CPC

- H10W 20/427: {Power or ground buses}
- H10W 72/00: Interconnections or connectors in packages
- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H05K 1/181: associated with surface mounted components
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 2201/10378: Interposers
- H05K 2201/10734: Ball grid array [BGA]; Bump grid array
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

## Claims

### Claim 1

An electronic package comprising:
a redistribution layer (RDL);
a die coupled to the RDL;
wherein the RDL includes a 3D interconnect structure for power and signal delivery to the die;
a chiplet on a second side of the RDL opposite the die; and
wherein the die includes a low performance logic and a high performance logic, and the chiplet is substantially directly underneath the low performance logic.

### Claim 2 (depends on 1)

The electronic package of claim 1, wherein 3D interconnect structure comprises:
a power bar underneath a plurality of contact pads, the power bar configured to supply a positive power supply to the die, wherein the die is bonded to the plurality of contact pads.

### Claim 3 (depends on 2)

The electronic package of claim 2, wherein the power bar is directly underneath and in electrical contact with the plurality of contact pads.

### Claim 4 (depends on 3)

The electronic package of claim 3, wherein the power bar is part of a power mesh plane.

### Claim 5 (depends on 3)

The electronic package of claim 3, further comprising a second power bar underneath a second plurality of contact pads, the second power bar to supply a negative power supply to the die, wherein the die is bonded to the second plurality of contact pads.

### Claim 6 (depends on 5)

The electronic package of claim 5, wherein the second power bar is directly underneath and in electrical contact with the second plurality of contact pads.

### Claim 7 (depends on 1)

The electronic package of claim 1, wherein the 3D interconnect structure includes a substantially vertical conductive line to provide a signal path between the chiplet and the low performance logic.

### Claim 8 (depends on 7)

The electronic package of claim 7, wherein the high performance logic is characterized by a power density that is at least twice a power density of the low performance logic.

### Claim 9 (depends on 7)

The electronic package of claim 7, wherein the chiplet comprises a multiple stack chiplet.

### Claim 10 (depends on 1)

The electronic package of claim 1, wherein the chiplet includes an integrated passive device.

### Claim 11 (depends on 1)

The electronic package of claim 1, further comprising a second die coupled to the RDL, wherein the chiplet is an electrical bridge between the first die and the second die.

### Claim 12 (depends on 1)

The electronic package of claim 1, wherein the chiplet comprises a power mesh plane.

### Claim 13 (depends on 12)

The electronic package of claim 12, further comprising a back side metal layer on a back side of the chiplet opposite the RDL.

### Claim 14 (depends on 13)

The electronic package of claim 13, further comprising a back side conductive bump coupled to the back side metal layer.

### Claim 15

An electronic package comprising:
a redistribution layer (RDL);
a die coupled to the RDL;
wherein the RDL includes a 3D interconnect structure for power and signal delivery to the die:
a chiplet, wherein the chiplet is at least partially directly underneath the die and comprises a power mesh plane;
wherein the 3D interconnect structure comprises a power bar underneath a plurality of contact pads, the power bar to supply a positive power supply to the die, wherein the die is bonded to the plurality of contact pads; and
wherein the power mesh plane is electrically coupled to the power bar.

### Claim 16 (depends on 15)

The electronic package of claim 15, wherein the chiplet comprises a power management unit.

### Claim 17

An electronic system comprising:
a circuit board, the circuit board including a negative power supply (Vss) landing pad, a positive power supply (Vdd) landing pad, and a plurality of signal landing pads;
an electronic package mounted on the circuit board and bonded to the Vss landing pad, the Vdd landing pad, and the plurality of signal landing pads;
wherein the electronic package includes:
a redistribution layer (RDL); and
a die on the RDL; and
a 3D interconnect structure for Vss, Vdd, and signal delivery to the die;
a chiplet on a second side of the RDL opposite the die, wherein the chiplet is at least partially directly underneath the die, and the chiplet comprises a power mesh plane;
wherein the 3D interconnect structure comprises: a power bar underneath a plurality of contact pads, the power bar coupled to the Vdd landing pad, wherein the die is bonded to the plurality of contact pads; and
wherein the power mesh plane is electrically coupled to the power bar.

### Claim 18 (depends on 17)

The electronic system of claim 17, wherein the power bar is directly underneath and in electrical contact with the plurality of contact pads.

### Claim 19 (depends on 17)

The electronic system of claim 17,
wherein the 3D interconnect structure comprises a first conductive line to provide a first signal path between the chiplet and the die.

### Claim 20 (depends on 17)

The electronic system of claim 17, further comprising:
an additional die, wherein the 3D interconnect structure comprises a second conductive line to provide a second signal path between the chiplet and the additional die.