# US 11,309,243 B2 · Package having different metal densities in different regions and manufacturing method thereof

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- Number: US 11,309,243 B2
- Document ID: US11309243B2
- Status: Granted
- Kind: B2
- Application number: 16/929,118
- Filed: 2020-07-15
- Published: 2021-03-04
- Granted: 2022-04-19
- Earliest claimed: 2019-08-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Jie Chen; Ming-Fa Chen; Sen-Bor Jan
- Web page: https://patentgrep.com/patent/US11309243B2

## CPC

- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 90/00: Package configurations
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/01: {Manufacture or treatment}
- H10W 72/019: {of bond pads}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/0198: {batch processes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/874: {On different surfaces}
- H10W 72/941: {Dispositions of bond pads}
- H10W 80/016: {Cleaning}
- H10W 80/041: {Thermally treating}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.

## Claims

### Claim 1

A package having a first region and a second region, comprising:
a first die;
a second die stacked on and bonded to the first die;
an encapsulant aside the second die, wherein at least a portion of the encapsulant is located in the second region; and
an inductor located in the second region, wherein a metal density in the first region is greater than a metal density in the second region.

### Claim 2 (depends on 1)

The package of claim 1, wherein the first die comprises:
a semiconductor substrate;
an interconnection structure over the semiconductor substrate;
a passivation layer over the interconnection structure;
a bonding layer over the passivation layer, wherein the bonding layer comprises bonding pads located in the first region and dummy bonding pads located in the second region, and a pattern density of the bonding pads is greater than a pattern density of the dummy bonding pads; and
bonding vias penetrating through the passivation layer, wherein the bonding vias electrically connect the interconnection structure and the bonding pads.

### Claim 3 (depends on 2)

The package of claim 2, wherein the inductor is embedded in the interconnection structure.

### Claim 4 (depends on 2)

The package of claim 2, wherein the dummy bonding pads are electrically floating.

### Claim 5 (depends on 2)

The package of claim 2, wherein a ratio of the pattern density of the dummy bonding pads to the pattern density of the bonding pads ranges from 1:2.7 to 1:27.

### Claim 6 (depends on 2)

The package of claim 2, wherein a spacing between two adjacent bonding pads is smaller than a spacing between two adjacent dummy bonding pads.

### Claim 7 (depends on 2)

The package of claim 2, wherein a width of each bonding pad is greater than a width of each dummy bonding pad.

### Claim 8 (depends on 1)

The package of claim 1, further comprising a redistribution structure over the second die and the encapsulant, wherein the inductor is embedded in the redistribution structure.

### Claim 9

A package, comprising:
a first die, comprising bonding pads and dummy bonding pads, wherein a pattern density of the bonding pads is greater than a pattern density of the dummy bonding pads;
a second die bonded to the first die, wherein the second die covers the bonding pads;
an encapsulant disposed on the first die, wherein the encapsulant laterally encapsulates the second die and covers the dummy bonding pads; and
an inductor over the dummy bonding pads.

### Claim 10 (depends on 9)

The package of claim 9, wherein the dummy bonding pads are electrically floating.

### Claim 11 (depends on 9)

The package of claim 9, wherein the inductor is embedded in the first die.

### Claim 12 (depends on 9)

The package of claim 9, further comprising a redistribution structure over the second die and the encapsulant, wherein the inductor is embedded in the redistribution structure.

### Claim 13 (depends on 9)

The package of claim 9, wherein the encapsulant is directly in contact with the dummy bonding pads and the inductor.

### Claim 14 (depends on 9)

The package of claim 9, wherein a spacing between two adjacent bonding pads is smaller than a spacing between two adjacent dummy bonding pads.

### Claim 15 (depends on 9)

The package of claim 9, wherein a width of each bonding pad is greater than a width of each dummy bonding pad.

### Claim 16

A manufacturing method of a package, comprising:
providing a wafer substrate having a first region and a second region, comprising:
forming first bonding pads having a first pattern density in the first region; and
forming dummy bonding pads having a second pattern density in the second region, wherein the first pattern density is greater than the second pattern density;
placing a die on the first region of the wafer substrate, wherein the die comprises second bonding pads hybrid bonded to the first bonding pads;
encapsulating the die by an encapsulant; and
forming an inductor over the second region.

### Claim 17 (depends on 16)

The method of claim 16, wherein at least a portion of the encapsulant is formed to be located over the second region.

### Claim 18 (depends on 17)

The method of claim 17, wherein the inductor is formed to be in direct contact with the portion of the encapsulant located over the second region.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
forming a redistribution structure over the die and the encapsulant, wherein the inductor is formed in the redistribution structure; and
forming conductive terminals over the redistribution structure.

### Claim 20 (depends on 16)

The method of claim 16, wherein the dummy bonding pads are formed to be electrically floating.