# US 11,309,236 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,236 B2 - Document ID: US11309236B2 - Status: Granted - Kind: B2 - Application number: 16/805,340 - Filed: 2020-02-28 - Published: 2021-03-11 - Granted: 2022-04-19 - Earliest claimed: 2019-09-10 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Minoru Kurata - Web page: https://patentgrep.com/patent/US11309236B2 ## CPC - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 74/01: Manufacture or treatment - H10W 90/00: Package configurations - H10W 72/073: {of die-attach connectors} - H10W 72/075: {of bond wires} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a pair of spacers disposed on the surface of a substrate, the spacers are a first height and spaced from each other at a first distance along a first direction. A first semiconductor chip is mounted on the substrate surface. The first semiconductor chip has a second height that is less than the first height. The first semiconductor chip can be connected to the substrate with bonding wires or the like. A second semiconductor chip is mounted on the spacers and spans the distance between the spacers. The second semiconductor chip is above at least a portion of the first semiconductor chip. A projecting section is provided on the surface of the substrate between the spacers in the first direction. The projecting section is between the first semiconductor chip and an outer edge of the substrate and protrudes upward from the surface of the substrate. ## Claims ### Claim 1 A semiconductor device, comprising: a first pair of spacers on a surface of a substrate, the spacers of the first pair having a first height and spaced from each other by a first distance along a first direction; a first semiconductor chip on the surface between the first pair of spacers in the first direction, the first semiconductor chip having a second height less than the first height and connected to the substrate with a plurality of bonding wires; a second semiconductor chip mounted on the first pair of spacers and spanning the first distance, the second semiconductor chip being above the first semiconductor chip; and a projecting section on the surface of the substrate between the first pair of spacers in the first direction, the projecting section being between the first semiconductor chip and an outer edge of the substrate and protruding upward from the surface to a third height. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the projecting section comprises a plurality of bonding wires spanning between different points on the surface of the substrate. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein each bonding wire in the projecting section extends substantially parallel to the second direction. ### Claim 4 (depends on 1) The semiconductor device according claim 1, wherein the projecting section comprises a solder resist. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the projecting section comprises a potting resin. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, further comprising: a packaging resin encapsulating the first semiconductor chip, the first pair of spacers, and the second semiconductor chip. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the third height is less than the first height. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the third height is less than or equal to the second height. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the substrate is a ball grid array package substrate. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, further comprising: a second pair of spacers mounted on the substrate, wherein the spacers of the second pair have the first height, at least a portion of the first semiconductor chip is between the spacers of the second pair in the first direction, and the first pair of spacers is spaced from the second pair of spacers on the substrate in a second direction crossing the first direction. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, further comprising: a third semiconductor chip mounted on the second pair of spacers and spanning a distance between the spacers of the second pair, the third semiconductor chip being above the first semiconductor chip. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, further comprising: another projecting section on the surface of the substrate between the second pair of spacers in the first direction and between the first semiconductor chip and the outer edge of the substrate and protruding upward from the surface to the third height. ### Claim 13 A semiconductor device, comprising: a substrate having a first surface; a first semiconductor chip mounted to the first surface of the substrate and connected to the substrate by a first plurality of bonding wires; a plurality of spacer chips mounted on the first surface of the substrate, each spacer chip in the plurality being between the first semiconductor chip and an outer edge of the substrate, each spacer chip being spaced from other spacer chip; a second semiconductor chip mounted on a first pair of spacer chips in the plurality of spacer chips, the first pair being spaced from each other in a first direction; and a projecting portion on the first surface of the substrate between the first pair of spacers in the first direction, the projecting portion being between the first plurality of bonding wires and the outer edge of the substrate in a second direction orthogonal to the first direction, the projecting portion protruding upward from the first surface of the substrate, wherein the first semiconductor chip extends from the first surface to a first height, and each spacer chip in the plurality extends from the first surface to a second height that is greater than the first height. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, further comprising: a third semiconductor chip mounted on a second pair of spacer chips in the plurality of spacer chips, the second pair being spaced from each other in the first direction, and spaced from the first pair in the second direction. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, further comprising: another projecting portion on the first surface of the substrate between the second pair of spacers in the first direction. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, wherein the projecting portion comprises a second plurality of bonding wires, each bonding wire in the second plurality being connected to two different points on the first surface of the substrate and spanning between the two different points on the first surface of the substrate. ### Claim 17 (depends on 13) The semiconductor device according to claim 13, wherein the projecting portion comprises a solder resist. ### Claim 18 (depends on 13) The semiconductor device according to claim 13, wherein the projecting portion comprises a potting resin. ### Claim 19 A semiconductor device, comprising: a planar substrate having a first surface; a first semiconductor chip mounted on the first surface and connected to the planar substrate by a first plurality of bonding wires, the first semiconductor chip having a substantially rectangular planar shape, the first semiconductor chip extending to a first height above the first surface in a first direction; a first spacer chip mounted on the first surface of the substrate between a first corner of the first semiconductor chip and an outer edge of the planar substrate; a second spacer chip mounted on the first surface of the substrate between a second corner of the first semiconductor chip and the outer edge of the planar substrate, the second spacer chip being spaced from the first spacer chip in a second direction along the first surface; a second semiconductor chip mounted on the first spacer chip and the second spacer chip, the second semiconductor chip spanning extending in the second direction from the first spacer chip to the second spacer chip while leaving a gap between a lower surface of the second semiconductor chip and the first surface of the substrate in the first direction; and a projecting section on the first surface of the substrate between the first and second spacers chips in the second direction, the projecting section being between the first plurality of bonding wires and the outer edge of the substrate in a third direction along the first surface crossing the second direction, the projecting section being disposed in the gap between the lower surface of second semiconductor chip and the first surface of the substrate. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, wherein the projecting section is formed of at least one of bonding wires, solder resist, and potting resin. ### Claim 21 A method of forming a semiconductor device, comprising: forming a first pair of spacers on a surface of substrate, the spacers of the first pair having a first height and being spaced from each other by a first distance along a first direction; placing a first semiconductor chip on the surface of the substrate; connecting the first semiconductor chip to the surface of the substrate with a first plurality of bonding wires; mounting a second semiconductor chip on the first pair of spacers, the second semiconductor chip spanning the first distance and being above the first semiconductor chip; and forming a projecting section on the surface of the substrate between the first pair of spacers in the first direction, the projecting section being between the first plurality of bonding wires and an outer edge of the substrate and protruding upward from the surface.