# US 11,309,235 B2 · Semiconductor module, electronic device, and printed wiring board > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,235 B2 - Document ID: US11309235B2 - Status: Granted - Kind: B2 - Application number: 16/901,117 - Filed: 2020-06-15 - Published: 2020-12-31 - Granted: 2022-04-19 - Earliest claimed: 2019-06-25 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Hideto Takahashi - Web page: https://patentgrep.com/patent/US11309235B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/652: Cross-sectional shapes - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 72/07253: {changes in shapes} - H10W 72/07254: {changes in dispositions} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/237: {Multiple bump connectors having different shapes} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor module includes a printed wiring board and a semiconductor device. The printed wiring board includes a plurality of lands bonded to the semiconductor device via solder, and a solder resist. The plurality of lands includes a first land positioned in a vicinity of an outer edge of the insulating substrate and including a first edge portion, a second edge portion, a third edge portion, and a fourth edge portion. The first edge portion and the second edge portion are configured not to overlap with the solder resist and the third edge portion and the fourth edge portion are configured to overlap with the solder resist. ## Claims ### Claim 1 A semiconductor module comprising: a printed wiring board; and a semiconductor device mounted on the printed wiring board, the printed wiring board comprising: an insulating substrate; a first land disposed on a main surface of the insulating substrate and bonded to the semiconductor device via solder; and a second land disposed on the main surface of the insulating substrate and bonded to the semiconductor device via solder; a solder resist disposed on the main surface of the insulating substrate and configured to cover one portion of each of the first land and the second land, wherein the first land comprises a first edge portion, a second edge portion, a third edge portion, and a fourth edge portion, wherein in a first direction, the first edge portion is positioned at one edge of the first land and the second edge portion is positioned at another edge of the first land, in the plan view, wherein in a second direction orthogonal to the first direction, the third edge portion is positioned at one edge of the first land and the fourth edge portion is positioned at another edge of the first land, in the plan view, and wherein in the plan view, the first edge portion and the second edge portion are configured not to overlap with the solder resist and the third edge portion and the fourth edge portion are configured to overlap with the solder resist, wherein the second land is positioned inside with respect to the first land, in the plan view, and wherein in the plan view, an area of a surface of the first land that does not overlap with the solder resist is larger than an area of a surface of the second land that does not overlap with the solder resist. ### Claim 2 (depends on 1) The semiconductor module according to claim 1, wherein the first land is positioned closer to an outer edge of the insulating substrate than the second land. ### Claim 3 (depends on 2) The semiconductor module according to claim 2, wherein in the plan view, the semiconductor device is rectangular and the first land is positioned in a vicinity of a corner portion of the semiconductor device. ### Claim 4 (depends on 3) The semiconductor module according to claim 3, wherein in the plan view, the first direction extends along a straight line passing through two opposite corners of the semiconductor device. ### Claim 5 (depends on 2) The semiconductor module according to claim 2, wherein, in the plan view, the first direction extends along a straight line passing through the first land and a center of the semiconductor device. ### Claim 6 (depends on 1) The semiconductor module according to claim 1, wherein the first land comprises a land body, a first projecting portion, and a second projecting portion, wherein the first projecting portion comprises the third edge portion and extends from the land body in the second direction, and wherein the second projecting portion comprises the fourth edge portion and extends from the land body in the second direction. ### Claim 7 (depends on 6) The semiconductor module according to claim 6, wherein in the plan view, the first projecting portion and the second projecting portion are positioned farther from the center of the semiconductor device than a center of the land body in the first direction. ### Claim 8 (depends on 6) The semiconductor module according to claim 6, wherein in the plan view, the land body is formed so as to widen toward a direction extending away from the center of the semiconductor device in the first direction. ### Claim 9 (depends on 1) The semiconductor module according to claim 1, wherein the semiconductor device comprises a third land bonded to the first land via solder, and wherein in the plan view, a center of the first land is positioned farther from the center of the semiconductor device than a center of the third land in the first direction. ### Claim 10 (depends on 1) The semiconductor module according to claim 1, wherein the first land is a dummy terminal. ### Claim 11 (depends on 1) An electronic device comprising: a housing; and the semiconductor module according to claim 1, wherein the semiconductor module is disposed in the housing. ### Claim 12 A printed wiring board on which a semiconductor device is mounted, the printed wiring board comprising: an insulating substrate; a first land disposed on a main surface of the insulating substrate and bonded to the semiconductor device via solder; a second land disposed on the main surface of the insulating substrate and bonded to the semiconductor device via solder; and a solder resist disposed on the main surface of the insulating substrate and configured to cover one portion of each of the first lands and the second land, wherein the first land comprises a first edge portion, a second edge portion, a third edge portion, and a fourth edge portion, wherein in a first direction passing through the first edge portion and a center of a mounting area in which the semiconductor device is mounted, the first edge portion is positioned at one edge of the first land and the second edge portion is positioned at another edge of the first land, in the plan view, wherein in a second direction orthogonal to the first direction, the third edge portion is positioned at one edge of the first land and the fourth edge portion is positioned at another edge of the first land, in the plan view, wherein in the plan view, the first edge portion and the second edge portion are configured not to overlap with the solder resist and the third edge portion and the fourth edge portion are configured to overlap with the solder resist, wherein the second land is positioned inside with respect to the first land, in the plan view, and wherein in the plan view, an area of a surface of the first land that does not overlap with the solder resist is larger than an area of a surface of the second land that does not overlap with the solder resist. ### Claim 13 A semiconductor module comprising: a printed wiring board; and a semiconductor device mounted on the printed wiring board, the printed wiring board comprising: an insulating substrate; a first land disposed on a main surface of the insulating substrate and bonded to the semiconductor device via solder; a second land disposed on a main surface of the insulating substrate and bonded to the semiconductor device via solder; and a solder resist disposed on the main surface of the insulating substrate and configured to cover one portion of each of the first land and the second land, wherein the first land comprises a first edge portion, a second edge portion, a third edge portion, and a fourth edge portion, wherein in a first direction, the first edge portion is positioned at one edge of the first land and the second portion is positioned at another edge of the first land, in the plan view, wherein in a second direction orthogonal to the first direction, the third edge portion is positioned at one edge of the first land and the fourth edge portion is positioned at another edge of the first land, in the plan view, wherein in the plan view, the first edge portion and the second edge portion are configured not to overlap with the solder resist and the third edge portion and the fourth edge portion are configured to overlap with the solder resist, and wherein the first land comprises a land body and the first land comprises at least one of a first projecting portion and a second projecting portion. ### Claim 14 (depends on 13) The semiconductor module according to claim 13, wherein the second land is positioned inside with respect to the first land, in the plan view, and wherein in the plan view, an area of a surface of the first land that does not overlap with the solder resist is larger than an area of a surface of the second land that does not overlap with the solder resist. ### Claim 15 (depends on 13) An electronic device, comprising: a housing; and the semiconductor module according to claim 13, wherein the semiconductor module is disposed in the housing. ### Claim 16 (depends on 13) The semiconductor module according to claim 13, wherein the first land comprises the land body, the first projecting portion, and the second projecting portion, wherein the first projecting portion comprises the third edge portion and extends from the land body in the second direction, and wherein the second projecting portion comprises the fourth edge portion and extends from the land body in the second direction.