# US 11,309,232 B2 · Semiconductor device

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- Number: US 11,309,232 B2
- Document ID: US11309232B2
- Status: Granted
- Kind: B2
- Application number: 16/630,690
- Filed: 2017-10-26
- Published: 2020-12-17
- Granted: 2022-04-19
- Earliest claimed: 2017-10-26
- Assignees: Shindengen Electric Manufacturing Co., Ltd.
- Applicants: Shindengen Electric Manufacturing Co., Ltd.
- Inventors: Soichiro Umeda; Takenori Ishioka
- Web page: https://patentgrep.com/patent/US11309232B2

## CPC

- H10W 70/427: {Bent parts}
- H10W 70/466: {Tape carriers or flat leads}
- H10W 70/468: {Circuit boards}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/01661: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01651)}
- H10W 72/07354: {changes in dispositions}
- H10W 72/076: {of strap connectors}
- H10W 72/07651: {characterised by changes in properties of the strap connectors during connecting}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/621: {Structures or relative sizes of strap connectors}
- H10W 72/631: {Shapes of strap connectors}
- H10W 72/634: {Cross-sectional shape}
- H10W 72/642: {being orthogonal to a side surface of the chip, e.g. in parallel arrangements}
- H10W 72/646: {the connected ends being on auxiliary connecting means on bond pads, e.g. on a bump connector}
- H10W 72/691: {Bond pads specially adapted therefor}
- H10W 72/853: {On the same surface}
- H10W 72/868: {Die-attach connectors and strap connectors}
- H10W 72/886: {Die-attach connectors and strap connectors}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes: a substrate; a semiconductor element that disposed on the upper surface of the substrate; a sealing portion that seals the substrate and the semiconductor element; a first lead frame that has one end in contact with a upper surface of the first conductive layer at an end extending in the side direction of the upper surface of the substrate in the sealing portion, and has the other end exposed from the sealing portion; a first conductive bonding material that bonds between the upper surface of the first conductive layer and the lower surface side of the one end portion of the first lead frame at the end portion of the substrate, and has electrical conductivity.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a semiconductor element that is mounted on the substrate;
a first lead terminal that is connected to a conductive layer on the substrate via a conductive bonding material; and
a sealing portion that seals the substrate and the semiconductor element,
wherein the first lead terminal includes:
a main body portion that is arranged in the sealing portion,
a first arch portion that is connected to the main body portion and is bent so as to project upward, and
a first bent portion that is connected to the first arch portion and is bent so as to project downward,
wherein notches are recessed in a width direction of the first bent portion and are formed on both side surfaces of the first bent portion in the width direction, the width direction being a direction of a width between the both side surfaces of the first bent portion, and
wherein the first lead terminal is connected to the conductive layer on the substrate, and wherein a lower end of the first bent portion comes into contact with the conductive layer on the substrate, and the conductive bonding material arranged on a surface of the conductive layer is bonded to a lower surface of the first bent portion and fills the notches.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the lower end of the first bent portion is in line contact with the conductive layer on the substrate.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein, in the first lead terminal, the upper end of the first arch portion protrudes upward from an upper surface of the main body portion, and the lower end of the first bent portion protrudes below a lower surface of the main body portion.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the first arch portion lets a stress applied to the first lead terminal escape to the surrounding sealing portion.