# US 11,309,228 B2 · Packaged semiconductor devices having enhanced thermal transport and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,228 B2 - Document ID: US11309228B2 - Status: Granted - Kind: B2 - Application number: 16/908,128 - Filed: 2020-06-22 - Published: 2021-04-08 - Granted: 2022-04-19 - Earliest claimed: 2019-10-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sunchul Kim; Taehun Kim; Pyoungwan Kim - Web page: https://patentgrep.com/patent/US11309228B2 ## CPC - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/778: {in encapsulations} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/00: Package configurations - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A packaged semiconductor device includes a package substrate, a first semiconductor device on the package substrate, and at least one second semiconductor device that extends on and partially covers the first semiconductor device. A heat dissipating insulation layer is provided as a coating on the first and second semiconductor devices. A conductive heat dissipation member is provided, which extends upwardly from the heat dissipating insulation layer and on portions of the first and second semiconductor devices. A protective member is provided on the package substrate, to cover the first and second semiconductor devices and the conductive heat dissipation member. This protective member includes a first covering portion, which covers an upper surface of the conductive heat dissipation member. ## Claims ### Claim 1 A packaged semiconductor device, comprising: a package substrate; a first semiconductor device, which is flip-chip mounted on the package substrate; at least one second semiconductor device on the first semiconductor device, which partially covers the first semiconductor device; a plurality of bonding wires electrically coupling the at least one second semiconductor device to said package substrate; a heat dissipating insulation layer, extending as a coating on at least portions of the first and second semiconductor devices and on the plurality of bonding wires; a conductive heat dissipation member extending upwardly from the heat dissipating insulation layer, on at least portions of the first and second semiconductor devices but not on the plurality of bonding wires; and a protective member on the package substrate, which covers the first and second semiconductor devices and the conductive heat dissipation member, said protective member including a first covering portion covering an upper surface of the conductive heat dissipation member, and a second covering portion that covers side surfaces of the first semiconductor device and side surfaces of the at least one second semiconductor device and encapsulates the plurality of wire bonds. ### Claim 2 (depends on 1) The packaged semiconductor device of claim 1, wherein the first covering portion includes a plate, which makes contact with the upper surface of the conductive heat dissipation member. ### Claim 3 (depends on 2) The packaged semiconductor device of claim 2, wherein the plate has a plurality of through holes therein; and wherein the conductive heat dissipation member has protrusions which extend at least partially into the through holes in the plate. ### Claim 4 (depends on 2) The packaged semiconductor device of claim 2, wherein the protective plate comprises at least one of a metal and a polymer material. ### Claim 5 (depends on 1) The packaged semiconductor device of claim 1, wherein an upper surface of the first covering portion is coplanar with an upper surface of the second covering portion. ### Claim 6 (depends on 1) The packaged semiconductor device of claim 1, wherein the first covering portion has a first thermal conductivity, and the second covering portion has a second thermal conductivity greater than the first thermal conductivity. ### Claim 7 (depends on 1) The packaged semiconductor device of claim 1, wherein the first covering portion has a thickness in a range from about 30 μm to about 150 μm. ### Claim 8 (depends on 1) The packaged semiconductor device of claim 1, wherein the conductive heat dissipation member comprises: a first conductive heat dissipation member arranged on the heat dissipating insulation layer located on a portion of the first semiconductor device exposed by the second semiconductor device; and a second conductive heat dissipation member arranged on the heat dissipation insulation layer on the second semiconductor device. ### Claim 9 (depends on 8) The packaged semiconductor device of claim 8, wherein the second conductive heat dissipation member is contiguous with the first conductive heat dissipation member. ### Claim 10 A packaged semiconductor device, comprising: a package substrate; a first semiconductor device arranged on the package substrate; at least one second semiconductor device on the first semiconductor device, which partially covers the first semiconductor device; a heat dissipating insulation layer extending as a coating on the first and second semiconductor devices; a first conductive heat dissipation member extending on a portion of the heat dissipating insulation layer, which is located on an underlying portion of the first semiconductor device exposed by the second semiconductor device; a second conductive heat dissipation member on another portion of the heat dissipation insulation layer that extends on the second semiconductor device; and a protective member on the package substrate, which covers the first and second semiconductor devices and the first conductive heat dissipation member, said protective member including a first covering portion, which covers upper surfaces of the first and second conductive heat dissipation members, and a second covering portion, which covers side surfaces of the first and second semiconductor devices and the first covering portion; wherein the upper surface of the first conductive heat dissipation member is coplanar with the upper surface of the second conductive heat dissipation member. ### Claim 11 (depends on 10) The packaged semiconductor device of claim 10, wherein the first covering portion includes a plate, which contacts the upper surfaces of the first and second conductive heat dissipation members. ### Claim 12 (depends on 11) The packaged semiconductor device of claim 11, wherein the plate has a plurality of through holes therein; and wherein the first conductive heat dissipation member has protrusions that extend at least partially into the through holes in the plate. ### Claim 13 (depends on 11) The packaged semiconductor device of claim 11, wherein the protective plate includes a material selected from a group consisting of metals and polymers. ### Claim 14 An electronic device, comprising: a substrate; a first electronic product arranged on the substrate; at least one second electronic product extending on, and partially covering, the first electronic product; a plurality of bonding wires electrically coupling the at least one second electronic product to said substrate; a heat dissipating insulation layer extending as a coating on the substrate, the first and second electronic products, and the plurality of bonding wires; a conductive heat dissipation member extending upwardly from the heat dissipating insulation layer, and on portions of the first and second electronic products; and a protective member on the substrate, which covers the first and second electronic products and the conductive heat dissipation member, said protective member including a first covering portion covering an upper surface of the conductive heat dissipation member and a second covering portion covering side surfaces of first and second electronic products and the first covering portion. ### Claim 15 (depends on 14) The electronic device of claim 14, wherein the first electronic product is configured to support higher maximum power consumption relative to the second electronic product. ### Claim 16 (depends on 14) The electronic device of claim 14, wherein the first covering portion includes a plate which makes contact with the upper surface of the conductive heat dissipation member. ### Claim 17 (depends on 16) The electronic device of claim 16, wherein the plate has a plurality of through holes therein; and wherein the conductive heat dissipation member has protrusions which extend at least partially into the through holes. ### Claim 18 (depends on 14) The electronic device of claim 14, wherein the first covering portion has a first thermal conductivity, and the second covering portion has a second thermal conductivity greater than the first thermal conductivity.