# US 11,309,226 B2 · Three-dimensional integrated circuit structures and methods of forming the same

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- Number: US 11,309,226 B2
- Document ID: US11309226B2
- Status: Granted
- Kind: B2
- Application number: 16/719,955
- Filed: 2019-12-18
- Published: 2021-06-24
- Granted: 2022-04-19
- Earliest claimed: 2019-12-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chia-Min Lin; Ching-Hua Hsieh; Chih-Wei Lin; Sheng-Hsiang Chiu; Sheng-Feng Weng; Yao-Tong Lai
- Web page: https://patentgrep.com/patent/US11309226B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 40/10: Arrangements for heating
- H10W 40/47: by flowing liquids, e.g. forced water cooling
- H10W 40/778: {in encapsulations}
- H10W 70/611: {for connecting multiple chips together}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

## Claims

### Claim 1

A three-dimensional integrated circuit (3DIC) structure, comprising:
a semiconductor package, disposed over and electrically connected to a first package substrate through a plurality of first bumps, wherein the semiconductor package comprises at least one semiconductor die and an encapsulation layer aside the semiconductor die;
a molded underfill layer, surrounding the plurality of first bumps and a sidewall of the semiconductor package and having a substantially planar top surface, wherein a coefficient of thermal expansion of the molded underfill layer is different from a coefficient of thermal expansion of the encapsulation layer of the semiconductor package; and
a thermal interface material disposed over the semiconductor package,
wherein the 3DIC structure further comprises a ring component surrounding the semiconductor package.

### Claim 2 (depends on 1)

The 3DIC structure of claim 1, wherein the semiconductor die has a first side close to the first package substrate and a second side away from the first package substrate, and the top surface of the molded underfill layer is higher than the second side of the semiconductor die.

### Claim 3 (depends on 1)

The 3DIC structure of claim 1, wherein the semiconductor die has a first side close to the first package substrate and a second side away from the first package substrate, and the molded underfill layer further covers a portion of the second side of the semiconductor die.

### Claim 4 (depends on 1)

The 3DIC structure of claim 1, wherein the molded underfill layer exposes a portion of the first package substrate.

### Claim 5 (depends on 1)

The 3DIC structure of claim 1, wherein the molded underfill layer further encapsulates at least one passive device aside the semiconductor package.

### Claim 6 (depends on 1)

The 3DIC structure of claim 1, wherein the semiconductor package further comprises a redistribution layer structure disposed between the semiconductor die and the first package substrate.

### Claim 7 (depends on 1)

The 3DIC structure of claim 1, wherein the coefficient of thermal expansion of the molded underfill layer is at least 1.5 times the coefficient of thermal expansion of the encapsulation layer.

### Claim 8 (depends on 1)

The 3DIC structure of claim 1, further comprising a cold plate or a fin-type heat sink disposed over the thermal interface material.

### Claim 9 (depends on 1)

The 3DIC structure of claim 1, wherein the encapsulation layer exposes a portion of the first package substrate.

### Claim 10

A three-dimensional integrated circuit (3DIC) structure, comprising:
a semiconductor package disposed over and electrically connected to a first package substrate, wherein the semiconductor package comprises at least one semiconductor die having a first side close to the first package substrate and a second side away from the first package substrate;
a passive device disposed over and electrically connected to the first package substrate, wherein the passive device and the semiconductor package are disposed laterally on the first package substrate;
a molded underfill layer disposed aside the semiconductor package and the passive device and having a top surface not lower than the second side of the semiconductor die; and
a clamp component configured to clamp the semiconductor package to a second package substrate below the first package substrate,
wherein the semiconductor package is bonded to the first package substrate through a plurality of first bumps, the first package substrate is bonded to the second package substrate through a plurality of second bumps, and a dimension of the plurality of first bumps is less than a dimension of the plurality of second bumps, and
wherein a capillary underfill layer surrounds the plurality of second bumps.

### Claim 11 (depends on 10)

The 3DIC structure of claim 10, wherein the molded underfill layer has a substantially planar top surface.

### Claim 12 (depends on 10)

The 3DIC structure of claim 10, wherein the molded underfill layer further covers a portion of the second side of the semiconductor die.

### Claim 13

A three-dimensional integrated circuit (3DIC) structure, comprising:
a semiconductor package, disposed over and electrically connected to a first package substrate through a plurality of first bumps, wherein the semiconductor package comprises semiconductor dies and an encapsulation layer aside and between the semiconductor dies;
a heat spreader, mounted on the semiconductor package and exposing a portion of the encapsulation layer; and
a molded underfill layer, surrounding the plurality of first bumps, a sidewall of the semiconductor package and a vertical side surface of the heat spreader.

### Claim 14 (depends on 13)

The 3DIC structure of claim 13, wherein a coefficient of thermal expansion of the molded underfill layer is different from a coefficient of thermal expansion of the encapsulation layer of the semiconductor package.

### Claim 15 (depends on 13)

The 3DIC structure of claim 13, further comprising a thermal interface material disposed between the semiconductor package and the heat spreader.

### Claim 16 (depends on 13)

The 3DIC structure of claim 13, wherein the encapsulation layer exposes a portion of the first package substrate.

### Claim 17 (depends on 13)

The 3DIC structure of claim 13, wherein the heat spreader is a cold plate with a plurality of cold pipes therein, and the cold pipes are arranged near a hot spot of the semiconductor package.

### Claim 18 (depends on 13)

The 3DIC structure of claim 13, further comprising a ring component surrounding the semiconductor package.

### Claim 19 (depends on 13)

The 3DIC structure of claim 13, further comprising a clamp component configured to clamp the semiconductor package to a second package substrate below the first package substrate.

### Claim 20 (depends on 19)

The 3DIC structure of claim 19, wherein the clamp component is in contact with a top surface of the molded underfill layer.