# US 11,309,225 B2 · Fan-out package structure and method of manufacturing the same

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- Number: US 11,309,225 B2
- Document ID: US11309225B2
- Status: Granted
- Kind: B2
- Application number: 16/714,801
- Filed: 2019-12-16
- Published: 2020-04-16
- Granted: 2022-04-19
- Earliest claimed: 2017-09-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Hsuan Tai; Chih-Hua Chen; Hao-Yi Tsai; Yu-Chih Huang; Chia-Hung Liu; Ting-Ting Kuo
- Web page: https://patentgrep.com/patent/US11309225B2

## CPC

- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.

## Claims

### Claim 1

A package structure, comprising:
a die;
a redistribution layer (RDL) structure disposed on and electrically connected to the die, wherein the RDL structure comprises a dielectric layer and a redistribution layer embedded in the dielectric layer;
a through integrated fan-out via (TIV) laterally aside the die and extending to contact a bottom surface and a sidewall of the redistribution layer of the RDL structure, wherein a portion of the dielectric layer is vertically sandwiched between the redistribution layer and the TIV; and
a conductive terminal, electrically connected to the die through the RDL structure and the TIV.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein a top surface of the TIV is higher than the bottom surface of the redistribution layer and lower than a topmost surface of the dielectric layer.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein a bottom corner of the dielectric layer is covered by the TIV.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the redistribution layer comprises a first seed layer and a conductive layer, and a portion of the conductive layer is separated from the first seed layer.

### Claim 5 (depends on 4)

The package structure of claim 4, wherein there is free of seed layer between the conductive terminal and the conductive layer of the redistribution layer.

### Claim 6 (depends on 1)

The package structure of claim 1, wherein the TIV comprises a second seed layer and a conductive post, the second seed layer and the conductive post are in physical contact with the conductive terminal.

### Claim 7 (depends on 6)

The package structure of claim 6, wherein a portion of the second seed layer is laterally between the redistribution layer and the conductive post, and vertically between the redistribution layer and the conductive post.

### Claim 8 (depends on 1)

The package structure of claim 1, wherein
the TIV comprises a first portion laterally aside the die, a second portion laterally aside the redistribution layer, and a third portion vertically between the first portion and the second portion; and
a width of the third portion is less than a width of the first portion and larger than a width of the second portion.

### Claim 9

A package structure, comprising:
a die;
a redistribution layer (RDL) structure connected to the die, wherein the RDL structure comprises a redistribution layer having a first seed layer and a conductive layer, the first seed layer is on the conductive layer; and
a through integrated fan-out via (TIV) laterally aside the die and extending into the RDL structure, the TIV comprises a second seed layer and a conductive post, the second seed layer is on the conductive post,
wherein the TIV has a top surface substantially coplanar with a top surface of the conductive layer of the redistribution layer.

### Claim 10 (depends on 9)

The package structure of claim 9, wherein the top surface of the TIV comprises a top surface of the conductive post and a top surface of the second seed layer coplanar with each other.

### Claim 11 (depends on 9)

The package structure of claim 9, wherein the first seed layer has a width less than a width of the conductive layer.

### Claim 12 (depends on 9)

The package structure of claim 9, further comprising a conductive terminal electrically connected to the die through the RDL structure and the TIV, wherein the conductive terminal has a bottom surface lower than a top surface of the first seed layer of the redistribution layer.

### Claim 13 (depends on 12)

The package structure of claim 12, wherein the bottom surface of the conductive terminal is in contact with the conductive layer and the conductive post.

### Claim 14 (depends on 9)

The package structure of claim 9, wherein the TIV covers a bottom corner of the redistribution layer.

### Claim 15 (depends on 9)

The package structure of claim 9, wherein the RDL structure further comprises a dielectric layer, and the redistribution layer is embedded in the dielectric layer, a portion of the dielectric layer is vertically sandwiched between the redistribution layer and the TIV.

### Claim 16 (depends on 15)

The package structure of claim 15, wherein the top surface of the TIV is lower than a top surface of the dielectric layer.

### Claim 17

A method of manufacturing a package structure, comprising:
forming an intermediate structure, comprising:
forming a RDL structure, wherein the RDL structure comprises a redistribution layer embedded in a dielectric layer, wherein the redistribution layer comprises a first seed layer and a conductive layer;
attaching a die on the RDL structure; and
forming a TIV laterally aside the die and extending into the RDL structure, the TIV comprises a second seed layer and a conductive post;
turning over the intermediate structure, such that the first seed layer is on the conductive layer, and the second seed layer is on the conductive post;
removing a portion of the first seed layer to expose a portion of the conductive layer; and
forming a conductive terminal to be in contact with the portion of the conductive layer,
wherein the TIV has a top surface substantially coplanar with a top surface of the conductive layer of the redistribution layer, and the RDL structure is connected to the die.

### Claim 18 (depends on 17)

The method of claim 17, further comprising removing a portion of the second seed layer to expose a portion of the conductive post, and the conductive terminal is further formed to be in contact with the portion of the conductive post.

### Claim 19 (depends on 17)

The method of claim 17, wherein the forming the TIV comprises:
patterning the dielectric layer to form a recess in the RDL structure, wherein the recess exposes a sidewall and a corner of the redistribution layer;
forming the second seed layer in the recess and on the dielectric layer; and
forming the conductive post on the second seed layer.

### Claim 20 (depends on 17)

The method of claim 17, wherein the second seed layer is formed to have a thickness substantially the same as a thickness of the first seed layer.