# US 11,309,224 B2 · Folded substrate for stacked integrated circuit devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,224 B2 - Document ID: US11309224B2 - Status: Granted - Kind: B2 - Application number: 16/214,284 - Filed: 2018-12-10 - Published: 2019-06-27 - Granted: 2022-04-19 - Earliest claimed: 2017-12-27 - Assignees: Shinko Electric Industries Co., Ltd. - Applicants: Shinko Electric Industries Co., Ltd. - Inventors: Yasuyoshi Horikawa; Yoshihiro Ihara; Yoshihiro Kita; Hikaru Tanaka - Web page: https://patentgrep.com/patent/US11309224B2 ## CPC - H10W 74/129: {forming a chip-scale package [CSP]} - H05K 1/144: {Stacked arrangements of planar printed circuit boards} - H05K 1/189: characterised by the use of flexible or folded printed circuits - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/688: {Flexible insulating substrates} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H05K 2201/055: Folded back on itself - H10W 44/234: {Arrangements for impedance matching} - H10W 72/01: {Manufacture or treatment} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A semiconductor device includes a flexible wiring substrate. The wiring substrate includes at least two mounting portions and at least one connecting portion. The mounting portions are stacked spaced apart from each other. Each connecting portion is bent to connect two mounting portions that are adjacent in a stacking direction. The semiconductor device further includes at least one semiconductor chip mounted on at least one of the at least two mounting portions and a plurality of conductive connecting members connecting the mounting portions to each other in the stacking direction. ## Claims ### Claim 1 A semiconductor device comprising: a wiring substrate that has flexibility and includes a first surface and a second surface located at opposite to the first surface, wherein the wiring substrate includes at least two mounting portions that are stacked spaced apart from each other, the at least two mounting portions including: a first mounting portion having first connecting pads at the first surface, and a second mounting portion adjacent to the first mounting portion in a stacking direction and having second connecting pads at the first surface and third connecting pads at the second surface, and at least one connecting portion, each of the at least one connecting portion being bent to connect two of the at least two mounting portions that are adjacent in the stacking direction; at least one semiconductor chip mounted on at least the first mounting portion of the at least two mounting portions; a plurality of conductive connecting members connecting the at least two mounting portions to each other in the stacking direction, the plurality of conductive connecting members being arranged between the at least two mounting portions without an interposer, each of the plurality of conductive connecting members having a height corresponding to a distance between adjacent two of the at least two mounting portions, the conductive connecting members including a set of first conductive connecting members, wherein each of the first conductive connecting members is directly connected to both a corresponding one of the first connecting pads and a corresponding one of the second connecting pads and extends across a gap between the corresponding one of the first connecting pads and the corresponding one of the second connecting pads in the stacking direction; and a set of second conductive connecting members, wherein each of the second conductive connecting members is directly connected to a corresponding one of the third connecting pads; and an encapsulation resin encapsulating all of the wiring substrate, the at least one semiconductor chip, and the plurality of conductive connecting members, wherein the wiring substrate includes a plurality of wiring layers and an insulation layer located between the plurality of wiring layers, and wherein the second mounting portion includes a first signal transmission path that extends straight through the second mounting portion in the stacking direction and is formed by the plurality of wiring layers electrically connected at a position overlapped with both of one of the first conductive connecting members and one of the second conductive connecting members. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein: the at least one semiconductor chip includes a first semiconductor chip mounted on the first mounting portion, and a second semiconductor chip mounted on the second mounting portion; the at least one connecting portion includes a first connecting portion connecting the first mounting portion and the second mounting portion; the wiring substrate includes a transmission line that extends from the first mounting portion via the first connecting portion to the second mounting portion to form a second signal transmission path, the first semiconductor chip is electrically connected to the second semiconductor chip by at least one of the first signal transmission path and the second signal transmission path. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the second signal transmission path includes at least one ground wiring line and a signal wiring line that is finer than the at least one ground wiring line. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the second signal transmission path includes two ground wiring lines and a signal wiring line located between the two ground wiring lines. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein the transmission line is a characteristic impedance-matched wiring line. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the at least one semiconductor chip is a bare chip and flip-chip mounted on at least one of the at least two mounting portions.