# US 11,309,223 B2 · Method of forming semiconductor device package having dummy devices on a first die

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- Number: US 11,309,223 B2
- Document ID: US11309223B2
- Status: Granted
- Kind: B2
- Application number: 16/889,348
- Filed: 2020-06-01
- Published: 2020-09-17
- Granted: 2022-04-19
- Earliest claimed: 2018-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Sung-Feng Yeh; Ming-Fa Chen; Hsien-Wei Chen; Hui-Wen Liu; Ching-Pin Yuan
- Web page: https://patentgrep.com/patent/US11309223B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 74/014: {using batch processing}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/232: {comprising connection or disconnection of parts of a device in response to a measurement}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 72/01215: {forming coatings}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01236: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/874: {On different surfaces}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/016: {Cleaning}
- H10W 80/163: {using active alignment, e.g. detecting marks and correcting position}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

## Claims

### Claim 1

A method comprising:
bonding a first die to a first carrier substrate;
stacking a plurality of second dies and a plurality of dummy devices on the first die to form a device stack;
bonding a second carrier substrate to the plurality of second dies and the plurality of dummy devices of the device stack;
removing the first carrier substrate from the first die;
forming conductive bumps on the first die;
testing the first die and the device stack using the conductive bumps of the first die; and
singulating the second carrier substrate and portions of the dummy devices to form a first device package.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first carrier substrate comprises first alignment marks, wherein the dummy devices comprise second alignment marks, and further comprising:
aligning the second alignment marks of the plurality of dummy devices with the first alignment marks of the first carrier substrate when stacking the dummy devices on the first die.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second carrier substrate comprises third alignment marks, and further comprising:
aligning the third alignment marks of the second carrier substrate with the second alignment marks of the plurality of dummy devices when bonding the second carrier substrate to the dummy devices.

### Claim 4 (depends on 3)

The method of claim 3, wherein a first subset of the second alignment marks have a first shape, and a second subset of the second alignment marks have a second shape, the first and second subsets of the second alignment marks being disposed in different layers of the device stack.

### Claim 5 (depends on 2)

The method of claim 2, wherein singulating the portions of the dummy devices comprises cutting the second alignment marks during singulation.

### Claim 6 (depends on 1)

The method of claim 1 further comprising:
aligning the first die and the second dies over the first carrier substrate without use of alignment marks.

### Claim 7

A method comprising:
bonding a logic device to a first carrier substrate, the first carrier substrate comprising first alignment marks;
bonding a first memory device to the logic device;
bonding a first dummy device to the logic device adjacent the first memory device, the first dummy device comprising second alignment marks, wherein bonding the first dummy device comprises aligning the second alignment marks with a first subset of the first alignment marks;
bonding a second memory device to the first memory device;
bonding a second dummy device to the first dummy device adjacent the second memory device, the second dummy device comprising third alignment marks, wherein bonding the second dummy device comprises aligning the third alignment marks with a second subset of the first alignment marks;
removing the first carrier substrate from the logic device;
after removing the first carrier substrate, testing the logic device, the first memory device, and the second memory device; and
after testing the logic device, the first memory device, and the second memory device, bonding the logic device to a package substrate.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first dummy device is one of a plurality of first dummy devices bonded to the logic device, the plurality of first dummy devices being disposed along two edges of the first memory device.

### Claim 9 (depends on 7)

The method of claim 7, wherein the first dummy device is one of a plurality of first dummy devices bonded to the logic device, the plurality of first dummy devices being disposed along four edges of the first memory device.

### Claim 10 (depends on 7)

The method of claim 7, wherein the first dummy device is a single dummy device surrounding four edges of the first memory device.

### Claim 11 (depends on 7)

The method of claim 7, wherein the second alignment marks and the third alignment marks do not overlap in a plan view.

### Claim 12 (depends on 7)

The method of claim 7, wherein the second alignment marks have a different shape than the third alignment marks.

### Claim 13 (depends on 7)

The method of claim 7 further comprising:
forming conductive bumps on the logic device, wherein the logic device, the first memory device, and the second memory device are tested using the conductive bumps, and wherein the logic device is bonded to the package substrate using the conductive bumps.

### Claim 14 (depends on 7)

The method of claim 7 further comprising:
singulating portions of the first dummy device and the second dummy device to form a device package.

### Claim 15 (depends on 14)

The method of claim 14, wherein singulating portions of the first dummy device and the second dummy device comprises cutting the second alignment marks and the third alignment marks during singulation.

### Claim 16 (depends on 7)

The method of claim 7 further comprising:
bonding a second carrier substrate to the second memory device and the second dummy device, the second carrier substrate comprising fourth alignment marks, wherein bonding the second carrier substrate comprises aligning the fourth alignment marks with a third subset of the first alignment marks.

### Claim 17

A method comprising:
bonding a first die to a first carrier substrate, the first die having a first function;
stacking second dies and dummy devices on the first die, each of the second dies having a second function;
removing the first carrier substrate from the first die to expose an active surface of the first die;
forming conductive bumps at the active surface of the first die;
testing the first die and the second dies using the conductive bumps; and
singulating the first die and portions of the dummy devices to form a first device package.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
before removing the first carrier substrate, bonding a second carrier substrate to the second dies and the dummy devices.

### Claim 19 (depends on 17)

The method of claim 17, wherein the dummy devices comprise alignment marks, and singulating the portions of the dummy devices comprises cutting the alignment marks.

### Claim 20 (depends on 17)

The method of claim 17, wherein the first die is a logic die, and stacking the second dies comprises:
placing a first memory die above the logic die, the first memory die comprising first conductive vias;
encapsulating the first memory die with a first encapsulant;
thinning the first encapsulant and the first memory die to expose the first conductive vias;
placing a second memory die above the first memory die, the second memory die comprising second conductive vias; and
encapsulating the second memory die with a second encapsulant, the second encapsulant and the second memory die not being thinned.