# US 11,309,222 B2 · Semiconductor chip with solder cap probe test pads > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,222 B2 - Document ID: US11309222B2 - Status: Granted - Kind: B2 - Application number: 16/556,105 - Filed: 2019-08-29 - Published: 2021-03-04 - Granted: 2022-04-19 - Earliest claimed: 2019-08-29 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Lei Fu; Milind S. Bhagavat; Chia-Hao Cheng - Web page: https://patentgrep.com/patent/US11309222B2 ## CPC - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01257: {by reflowing} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/29: Bond pads specially adapted therefor - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad. ## Claims ### Claim 1 A semiconductor chip, comprising: a substrate; plural input/output (I/O) structures on the substrate; plural test pads on the substrate, each of the test pads including a first conductor pad and a first solder cap on the first conductor pad, wherein the first solder cap is configured, without reflow, to receive a test probe; and a polymer structure positioned over the first solder cap without reflow. ### Claim 2 (depends on 1) The semiconductor chip of claim 1, wherein each of the test pads includes a plating seed layer between the first solder cap and the first conductor pad. ### Claim 3 (depends on 1) The semiconductor chip of claim 1, wherein the I/O structures comprise microbumps. ### Claim 4 (depends on 3) The semiconductor chip of claim 3, wherein each of the microbumps comprises a pillar portion, a barrier layer on the pillar portion, a solderable layer on the barrier layer and a second solder cap on the solderable layer. ### Claim 5 (depends on 4) The semiconductor chip of claim 4, wherein the semiconductor chip includes plural second conductor pads, each of the microbumps includes a plating seed layer positioned between one of the second conductor pads and the pillar portion. ### Claim 6 (depends on 1) The semiconductor chip of claim 1, wherein the polymer structure is infused with photoactive compounds and formed using photolithography. ### Claim 7 (depends on 1) The semiconductor chip of claim 1, comprising a photoresist mask structure positioned over each of the test pads. ### Claim 8 A method of manufacturing a semiconductor chip having a substrate, comprising: fabricating plural input/output (I/O) structures on the substrate; fabricating plural test pads on the substrate, each of the test pads including a first conductor pad and a first solder cap on the first conductor pad, wherein the first solder cap is configured, without reflow, to receive a test probe; and fabricating a polymer structure over the first solder cap without reflow. ### Claim 9 (depends on 8) The method of claim 8, comprising fabricating a plating seed layer between the first solder cap and the first conductor pad of each of the test pads. ### Claim 10 (depends on 8) The method of claim 8, wherein the I/O structures comprise microbumps. ### Claim 11 (depends on 10) The method of claim 10, wherein each of the microbumps comprises a pillar portion, a barrier layer on the pillar portion, a solderable layer on the barrier layer and a second solder cap on the solderable layer. ### Claim 12 (depends on 11) The method of claim 11, comprising fabricating plural second conductor pads on the substrate and a plating seed layer on each of the conductor pads and one of the pillar portions on each of the plating seed layers. ### Claim 13 (depends on 8) The method of claim 8, wherein the polymer structure is infused with photoactive compounds and formed using photolithography. ### Claim 14 (depends on 8) The method of claim 8, comprising fabricating a photoresist mask structure over each of the test pads. ### Claim 15 A method of testing a semiconductor chip, the semiconductor chip having a substrate, plural first conductor pads on the substrate and plural test pads on the substrate each including a second conductor pad and a first solder cap on the second conductor pad, the method comprising: without reflow, contacting one or more probe pins on one or more of the first solder caps; probe testing the semiconductor chip; and fabricating a polymer structure over the one or more first solder caps without reflow. ### Claim 16 (depends on 15) The method of claim 15, wherein the one or more probe pins have a flat end to contact the one or more first solder caps. ### Claim 17 (depends on 15) The method of claim 15, wherein the polymer structure is infused with photoactive compounds and formed using photolithography after probe testing. ### Claim 18 (depends on 15) The method of claim 15, comprising fabricating a photoresist mask structure over each of the test pads after probe testing. ### Claim 19 (depends on 15) The method of claim 15, wherein the semiconductor chip comprises part of a semiconductor wafer. ### Claim 20 (depends on 15) The method of claim 15, comprising fabricating plural input/output structures on each of the first conductor pads after probe testing.