# US 11,309,220 B2 · Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor

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- Number: US 11,309,220 B2
- Document ID: US11309220B2
- Status: Granted
- Kind: B2
- Application number: 15/676,005
- Filed: 2017-08-14
- Published: 2019-02-14
- Granted: 2022-04-19
- Earliest claimed: 2017-08-14
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Chanro Park; Ruilong Xie; Min Gyu Sung
- Web page: https://patentgrep.com/patent/US11309220B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 84/0158: {the components including FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

## Claims

### Claim 1

A method, comprising:
forming a plurality of fins on a substrate, wherein each fin comprises a first side, a second side, and a hard mask on a top of the fin, wherein the hard mask has a top surface;
forming a bottom spacer on the substrate and between each pair of adjacent fins, wherein the bottom spacer is in contact with the first side and the second side of each fin;
forming a gate structure in contact with the first side of each fin from a first height below the top surface of the hard mask to the bottom spacer and in contact with the second side of each fin from the first height to the bottom spacer, wherein said gate structure comprises a high-k dielectric layer in contact with said fin, a work function metal (WFM) layer in contact with said high-k dielectric layer, and a nitride layer in contact with said WFM layer;
forming a side spacer in contact with the first side of each fin from the top surface of the hard mask to the first height and in contact with the second side of each fin from the top surface to the first height;
forming at least one layer above said bottom spacer and between said fins; and
forming an opening in said at least one layer between said fins by an etching process, wherein said side spacer protects said gate structure from said etching process.

### Claim 2 (depends on 1)

The method of claim 1, wherein said substrate comprises silicon or silicon germanium and said at least one layer above said bottom spacer comprises an oxide layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein said side spacer comprises a nitride layer in contact with said fin or said hard mask on said fin, an oxide liner in contact with said nitride layer, and a nitride spacer in contact with said oxide liner.

### Claim 4 (depends on 1)

The method of claim 1, wherein said side spacer has a first width, said gate structure has a second width, and said first width is greater than said second width.

### Claim 5 (depends on 1)

The method of claim 1, wherein said forming an opening comprises performing a reactive ion etch (ME) in forming the opening.

### Claim 6 (depends on 1)

The method of claim 1, wherein said plurality of fins is a first plurality of fins and has a first end, and the method further comprises:
forming a second plurality of fins, wherein said second plurality of fins has a second end proximate said first end; and
patterning at least one contact contacting both said first end and said second end.

### Claim 7 (depends on 1)

The method of claim 1, further comprising electrically isolating said gate structure of a first fin from said gate structure of a second fin by filling said opening with an oxide.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
removing said side spacer from each fin; and
forming a second source/drain (S/D) region above said plurality of fins.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming a first source/drain (S/D) region on said substrate, wherein said plurality of fins are formed above said first S/D region.

### Claim 10

A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device comprising at least one field effect transistor (FET); and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system;
wherein said semiconductor device processing system is adapted to:
form a plurality of fins on a substrate, wherein each fin comprises a first side, a second side, and a hard mask on a top of the fin, wherein the hard mask has a top surface;
form a bottom spacer on the substrate and between each pair of adjacent fins, wherein the bottom spacer is in contact with the first side and the second side of each fin;
form a gate structure in contact with the first side of each fin from a first height below the top surface of the hard mask to the bottom spacer and in contact with the second side of each fin from the first height to the bottom spacer, wherein said gate structure comprises a high-k dielectric layer in contact with said fin, a work function metal (WFM) layer in contact with said high-k dielectric layer, and a nitride layer in contact with said WFM layer;
form a side spacer in contact with the first side of each fin from the top surface of the hard mask to the first height and in contact with the second side of each fin from the top surface to the first height;
form at least one layer above said bottom spacer and between said fins; and
form an opening in said at least one layer between said fins by an etching process, wherein said side spacer protects said gate structure from said etching process.

### Claim 11 (depends on 10)

The system of claim 10, further comprising:
a design unit configured to generate a design comprising a definition for a plurality of processes and a definition for an operation of a FET device that comprises a plurality of fins, wherein data from said design unit is used by said process controller to control an operation of said semiconductor device processing system.

### Claim 12 (depends on 10)

The system of claim 10, wherein said semiconductor device processing system is further adapted to:
form a first source/drain (S/D) region on a substrate, wherein said plurality of fins is formed above said first S/D region.

### Claim 13 (depends on 12)

The system of claim 12, wherein said semiconductor device processing system is further adapted to:
remove said side spacer from each fin; and
form a second source/drain (S/D) region above said plurality of fins.