# US 11,309,217 B2 · Contact plug and method of formation

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- Number: US 11,309,217 B2
- Document ID: US11309217B2
- Status: Granted
- Kind: B2
- Application number: 15/909,682
- Filed: 2018-03-01
- Published: 2019-09-05
- Granted: 2022-04-19
- Earliest claimed: 2018-03-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ya-Huei Li; Li-Wei Chu; Yu-Hsiang Liao; Hung-Yi Huang; Chih-Wei Chang; Ching-Hwanq Su
- Web page: https://patentgrep.com/patent/US11309217B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/066: {by forming silicides of refractory metals}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/48: Insulating materials thereof
- H10D 30/0212: {using self-aligned silicidation}
- H10P 50/283: {by chemical means}
- H10P 52/403: {of conductive or resistive materials}
- H10P 76/2041: {Photolithographic processes}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.

## Claims

### Claim 1

A method for forming a semiconductor contact plug, the method comprising:
forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region extending into the substrate and having side portions and a bottom portion that exposes the substrate;
forming a dielectric barrier layer in the contact region to cover the side portions of the contact region;
removing an upper portion of the dielectric barrier layer to expose an upper sidewall of the dielectric stack;
forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region, wherein the conductive blocking layer has a lateral surface lower than a top surface of the dielectric stack and higher than a topmost surface of the dielectric barrier layer;
forming a conductive layer over the conductive blocking layer;
forming a conductive barrier layer over the conductive layer;
performing a first annealing process to form a silicide region in the substrate beneath the conductive layer; and
performing a second annealing process by diffusing a portion of the conductive layer into the substrate to increase a thickness of the silicide region in the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first annealing process is performed after forming the conductive layer and the second annealing process is performed after forming the conductive barrier layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the conductive blocking layer further comprises forming the conductive blocking layer with a thickness of less than 10 Å.

### Claim 4 (depends on 1)

The method of claim 1, comprising forming the conductive layer over the conductive blocking layer, and forming the conductive barrier layer over the conductive layer in the contact region with a total thickness of the three layers along the side portions of the contact region being less than 20 Å.

### Claim 5 (depends on 1)

The method of claim 1, wherein the conductive blocking layer that is formed in the contact region by a low temperature process comprises at least one of titanium (Ti), nickel (Ni), tungsten (W), cobalt (Co), or platinum (Pt).

### Claim 6 (depends on 1)

The method of claim 1, wherein the dielectric barrier layer that is formed in the contact region to cover the side portions and the bottom portion comprises at least one of SiN, SiCN, SiC, SiON, and AlOx.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a conductive core in the contact region that is in contact with the conductive barrier layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the conductive blocking layer and the conductive layer are made of the same material.

### Claim 9

A semiconductor device, comprising:
a dielectric stack formed on a substrate;
a contact region formed within the dielectric stack and extending into the substrate, the contact region having side portions and a bottom portion;
a dielectric barrier layer formed on the side portions of the contact region;
a conductive blocking layer formed along the side portions of the contact region over the dielectric barrier layer and the dielectric stack, wherein a topmost surface of the dielectric barrier layer is lower than a topmost surface of the conductive blocking layer, and the topmost surface of the conductive blocking layer is substantially level with a top surface of the dielectric stack, and a bottommost surface of the dielectric barrier layer is substantially level with a bottommost surface of the conductive blocking layer, and wherein the conductive blocking layer has a lateral surface lower than the top surface of the dielectric stack and higher than the topmost surface of the dielectric barrier layer;
a conductive layer formed along the side portions and bottom portion of the contact region over the conductive blocking layer in the contact region;
a conductive barrier layer formed on the conductive layer in the contact region, wherein a bottom surface of the conductive blocking layer is substantially level with a top surface of the substrate, and the conductive layer and the conductive barrier layer extend into the substrate;
a conduct core over the conductive barrier layer in the contact region; and
a silicide region located in the substrate beneath the conductive layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the conductive blocking layer has a thickness of less than 10 Å.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the conductive blocking layer is at least one of titanium (Ti), nickel (Ni), tungsten (W), cobalt (Co), or platinum (Pt).

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the conductive layer is formed over the conductive blocking layer, and the conductive barrier layer is arranged over the conductive layer, and the total thickness of three layers along the side portions of the contact region are less than 20 Å.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the dielectric barrier layer formed on the side portions of contact region is at least one of SiN, SiCN, SiC, SiON, and AlOx.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the conductive layer formed over the conductive blocking layer in the contact region is at least one of titanium (Ti), nickel (Ni), tungsten (W), cobalt (Co), or platinum (Pt).

### Claim 15 (depends on 9)

The method of claim 9, wherein the conductive blocking layer and the conductive layer are made of the same material.

### Claim 16

A method for forming a semiconductor contact plug, the method comprising:
depositing a dielectric stack over a substrate;
forming a contact region in the dielectric stack, the contact region extending into the substrate and having side portions and a bottom portion that exposes the substrate;
forming a dielectric barrier layer along the side portions of the contact region;
depositing a first metal layer in the contact region over the dielectric barrier layer and the dielectric stack to cover the side portions and bottom portion of the contact region, wherein the first metal layer has a lateral surface lower than a top surface of the dielectric stack and higher than a topmost surface of the dielectric barrier layer;
depositing a second metal layer over the first metal layer;
depositing a conductive barrier layer over the second metal layer; and
performing a first annealing process to form a silicide region in the substrate; and
performing a second annealing process by diffusing a portion of the second metal layer into the substrate to increase a thickness of the silicide region in the substrate, wherein the first annealing process is performed before the formation of the conductive barrier layer, and the second annealing process is performed after the formation of the conductive barrier layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first annealing process is performed after the formation of the second metal layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein depositing the first metal layer further comprises depositing the first metal layer at a temperature that is below 30° C. and with a thickness of less than 10 Å.

### Claim 19 (depends on 16)

The method of claim 16, further comprising forming a dielectric barrier layer along the side portions of the contact region, wherein the first metal layer is formed over the dielectric barrier layer and the dielectric stack.

### Claim 20 (depends on 16)

The method of claim 16, further comprising depositing the second metal layer over the first metal layer, and depositing the conductive barrier layer over the second metal layer in the contact region with a total thickness of three layers along the side portions of the contact region being less than 20 Å.