# US 11,309,216 B2 · Large grain copper interconnect lines for MRAM

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- Number: US 11,309,216 B2
- Document ID: US11309216B2
- Status: Granted
- Kind: B2
- Application number: 16/773,939
- Filed: 2020-01-27
- Published: 2021-07-29
- Granted: 2022-04-19
- Earliest claimed: 2020-01-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alexander Reznicek; Oleg Gluschenkov; Yasir Sulehria; Devika Sil
- Web page: https://patentgrep.com/patent/US11309216B2

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10W 20/033: {in openings in dielectrics}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

## Claims

### Claim 1

A method of forming large grain copper bitlines for an electronic structure, comprising:
obtaining an MRAM structure including:
a device wafer comprising electronic devices;
a metallized layer over the device wafer and including bottom electrodes therein, the bottom electrodes being electrically connected to the electronic devices; and
vertical pillars having sidewalls above the metallized layer, the vertical pillars each including a magnetic tunnel junction and a top electrode;
forming a copper bitline exhibiting a copper wire size effect over the top electrodes, the copper bitline having a width of forty nanometers or less, an area of three thousand square nanometers or less, and copper grains having relatively small sizes with respect to the width of the copper bitline;
laser annealing the copper bitline, thereby melting the copper bitline; and
recrystallizing the copper bitline during a cool down period following the laser annealing, thereby forming relatively large grains therein and reducing the copper wire size effect of the copper bitline formed over the top electrodes.

### Claim 2 (depends on 1)

The method of claim 1, wherein the relatively large grains formed by recrystallizing the copper bitline are vertically aligned with the vertical pillars and include grain boundaries that are mostly over a plurality of spaces between the vertical pillars, and further wherein the vertical pillars have a pitch of sixty nanometers or more along the copper bitline.

### Claim 3 (depends on 1)

The method of claim 1, wherein the relatively large grains have an average grain size larger than 0.06 μm after recrystallizing the copper bitline, further wherein recrystallizing the copper bitline includes reducing the copper wire size effect by half or more.

### Claim 4 (depends on 3)

The method of claim 3, wherein the copper bitline includes copper at an atomic concentration of at least ninety percent.

### Claim 5 (depends on 4)

The method of claim 4, wherein the MRAM structure further includes a dielectric layer between each of the vertical pillars, the relatively large grains including grain boundaries extending mostly over the dielectric layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the laser annealing is conducted at a laser anneal density of from 0.05 to 3 J/cm2.

### Claim 7 (depends on 6)

The method of claim 6, wherein the tunneling magnetoresistance of each magnetic tunnel junction is substantially the same prior to and subsequent to recrystallizing the copper bitline.

### Claim 8 (depends on 6)

The method of claim 6, wherein the MRAM structure further includes a metal liner immiscible in liquid copper and extending over the top electrodes and the dielectric layer, further forming the copper bitline directly on the metal liner.

### Claim 9 (depends on 1)

The method of claim 1, wherein the vertical pillars have a pitch along the copper bitline at least sixty nanometers.

### Claim 10 (depends on 9)

The method of claim 9, wherein laser annealing the copper bitline comprises multiple consecutive copper melt anneals.

### Claim 11

A method of forming large grain copper bitlines for an electronic structure, comprising:
obtaining an MRAM structure including:
vertical pillars having a pitch of sixty nanometers or more, each of the vertical pillars including a magnetic tunnel junction and a top electrode;
a plurality of spaces respectively between and separating each of the vertical pillars; and
a dielectric layer filling each of the plurality of spaces between the vertical pillars;
forming a copper bitline over the top electrodes and along the pitch of the vertical pillars and extending over the spaces between the vertical pillars, the copper bitline having a width of forty nanometers or less, an area of three thousand square nanometers or less, and copper grains having relatively small sizes with respect to the width of the copper bitline;
laser annealing the copper bitline, thereby melting the copper bitline; and
recrystallizing the copper bitline during a cool down period following the laser annealing, thereby forming relatively large grains therein that are vertically aligned, respectively, with the vertical pillars and having grain boundaries located mostly over the dielectric layer in the spaces between the vertical pillars.

### Claim 12 (depends on 11)

The method of claim 11, wherein laser annealing the copper bitline comprises multiple consecutive copper melt anneals and recrystallizing the copper bitline includes multiple cool down periods between the consecutive copper melt anneals.

### Claim 13 (depends on 11)

The method of claim 11, wherein the laser annealing is conducted at a laser anneal density of from 0.05 to 3 J/cm2.

### Claim 14 (depends on 11)

The method of claim 11, wherein the MRAM structure further includes a metal liner immiscible in liquid copper and extending over the top electrodes and the dielectric layer, further including forming the copper bitline directly on the metal liner.

### Claim 15 (depends on 14)

The method of claim 14, wherein laser annealing the copper bitline includes causing an anneal at or below 1150° C., the metal liner remaining in a solid state during laser annealing.