# US 11,309,213 B2 · Method for manufacturing semiconductor structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,309,213 B2
- Document ID: US11309213B2
- Status: Granted
- Kind: B2
- Application number: 16/940,246
- Filed: 2020-07-27
- Published: 2020-11-12
- Granted: 2022-04-19
- Earliest claimed: 2017-11-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Yu-Hsiang Liao; Ya-Huei Li; Li-Wei Chu; Chun-Wen Nieh; Hung-Yi Huang; Chih-Wei Chang; Ching-Hwanq Su
- Web page: https://patentgrep.com/patent/US11309213B2

## CPC

- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/047: {by introducing additional elements therein}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, the method comprising:
forming a trench in a dielectric layer;
forming a liner conductive layer in the trench, wherein the liner conductive layer comprises a first conductive portion over a bottom of the trench, and a second conductive portion over a sidewall of the trench;
forming a liner sacrificial layer over the liner conductive layer, wherein the liner sacrificial layer comprises a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion; and
removing the first sacrificial portion and the second sacrificial portion of the liner sacrificial layer, and the second conductive portion of the liner conductive layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the liner sacrificial layer is formed over the liner conductive layer in an in-situ manner.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first sacrificial portion and the second sacrificial portion of the liner sacrificial layer, and the second conductive portion of the liner conductive layer are removed in an in-situ manner.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first thickness of the first sacrificial portion is measured along a first direction substantially parallel to a depth direction of the trench.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second thickness of the second sacrificial portion is measured along a second direction different from the first direction.

### Claim 6 (depends on 1)

The method of claim 1, wherein the liner conductive layer comprises a silicide layer and a capping layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the forming of the liner conductive layer further comprises forming the silicide layer in the trench.

### Claim 8 (depends on 6)

The method of claim 6, wherein at least a portion of the capping layer remains over the bottom of the trench after the removing the first sacrificial portion and the second sacrificial portion of the liner sacrificial layer, and the second conductive portion of the liner conductive layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming a conductive via in the trench after the removing the first sacrificial portion and the second sacrificial portion of the liner sacrificial layer, and the second conductive portion of the liner conductive layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the conductive via is electrically connected to the first conductive portion of the liner conductive layer.

### Claim 11

A method for manufacturing a semiconductor structure, the method comprising:
providing a semiconductor substrate having a doped semiconductor region;
forming a dielectric layer over the semiconductor substrate;
forming a trench exposing the doped semiconductor region in the dielectric layer, wherein the trench includes a sidewall;
forming a capping layer in the trench;
forming a sacrificial layer over the capping layer; and
removing the sacrificial layer along with a portion of the capping layer from the sidewall of the trench.

### Claim 12 (depends on 11)

The method of claim 11, wherein a first thickness of the sacrificial layer over the doped semiconductor region is greater than a second thickness of the sacrificial layer over the sidewall of the trench.

### Claim 13 (depends on 11)

The method of claim 11, further comprising forming a barrier layer over the sidewall of the trench.

### Claim 14 (depends on 13)

The method of claim 13, wherein the doped semiconductor region of the semiconductor substrate is exposed through the barrier layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein the barrier layer is formed before the forming of the capping layer.

### Claim 16 (depends on 11)

The method of claim 11, further comprising forming a conductive via in the trench after the removing the sacrificial layer along with the portion of the capping layer from the sidewall of the trench.

### Claim 17

A method for manufacturing a semiconductor structure, the method
comprising:
forming a dielectric layer having a trench, wherein the trench includes a bottom and a sidewall;
forming a conductive layer in the trench, wherein the conductive layer comprises a conductive portion over the sidewall of the trench;
forming a sacrificial layer over the conductive layer, wherein the forming of the sacrificial layer comprises:
forming a metal layer over the conductive layer in a physical vapor deposition chamber; and
exposing the metal layer to an oxygen-containing environment to form a metal oxide layer as the sacrificial layer, wherein a first thickness of the sacrificial layer over the bottom of the trench is thicker than a second thickness of the sacrificial layer over the sidewall of the trench; and
removing the sacrificial layer along with the conductive portion from the sidewall of the trench.

### Claim 18 (depends on 17)

The method of claim 17, wherein the conductive layer comprises a capping layer and a silicide layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the silicide layer is formed at the bottom of the trench.

### Claim 20 (depends on 17)

The method of claim 17, further comprising forming a barrier layer over the sidewall of the trench, wherein the barrier layer is in contact with the dielectric layer.