# US 11,309,211 B2 · Method for forming semiconductor device with buried gate structure

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- Number: US 11,309,211 B2
- Document ID: US11309211B2
- Status: Granted
- Kind: B2
- Application number: 16/874,223
- Filed: 2020-05-14
- Published: 2021-11-18
- Granted: 2022-04-19
- Earliest claimed: 2020-05-14
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chun-Chi Lai
- Web page: https://patentgrep.com/patent/US11309211B2

## CPC

- H10D 64/027: {by etching at gate locations}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10D 62/299: {having lateral doping variations (IGFETs having lightly doped source or drain extensions H10D30/601)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/032: {of conductive barrier, adhesion or liner layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for forming a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate;
forming a gate dielectric layer lining the trench; and
forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, wherein forming the gate electrode layer comprises:
performing a first deposition process to deposit a gate electrode material in the trench and over the gate dielectric layer and the top surface of the semiconductor, wherein the gate electrode material in the trench includes top portions close to the top surface of the semiconductor and bottom portions away from the top surface of the semiconductor, wherein a thickness of the top portions is greater than a thickness of the bottom portions;
performing a first etching process on the gate electrode material after the first deposition process; and
performing a second deposition process after the first etching process.

### Claim 2 (depends on 1)

The method for forming a semiconductor device of claim 1, wherein a gap is surrounded by the gate electrode material.

### Claim 3 (depends on 2)

The method for forming a semiconductor device of claim 2, wherein the gap is widened during the first etching process.

### Claim 4 (depends on 2)

The method for forming a semiconductor device of claim 2, wherein the gate electrode material has a thickness over the top surface of the semiconductor substrate before the first etching process, and the thickness of the gate electrode material is reduced during the first etching process.

### Claim 5 (depends on 1)

The method for forming a semiconductor device of claim 1, wherein forming the gate electrode layer further comprises:
performing a second etching process after the second deposition process, wherein the first etching process and the second etching process are dry etching processes; and
performing a third deposition process after the second etching process.

### Claim 6 (depends on 1)

The method for forming a semiconductor device of claim 1, further comprising:
etching the gate electrode layer to form a recess over a remaining portion of the gate electrode layer such that a top surface of the remaining portion of the gate electrode layer is lower than the top surface of the semiconductor substrate; and
forming a dielectric cap layer to cover the remaining portion of the gate electrode layer and the top surface of the semiconductor substrate.

### Claim 7 (depends on 6)

The method for forming a semiconductor device of claim 6, further comprising:
removing a portion of the dielectric capping layer to expose a source/drain (S/D) region adjacent to the remaining portion of the gate electrode layer; and
forming a bit line structure over the S/D region.

### Claim 8

A method for forming a semiconductor device, comprising:
forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate;
forming a gate dielectric layer lining the trench; and
forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, wherein forming the gate electrode layer comprises:
depositing a first gate electrode material in the trench and over the gate dielectric layer and the top surface of the semiconductor substrate, wherein a first gap is surrounded by the first gate electrode material, wherein the gate electrode material in the trench includes top portions close to the top surface of the semiconductor and bottom portions away from the top surface of the semiconductor, wherein a thickness of the top portions is greater than a thickness of the bottom portions; and
etching the first gate electrode material to widen the first gap such that a first opening is surrounded by a remaining portion of the first gate electrode material, wherein a top width of the first opening is greater than a top width of the first gap.

### Claim 9 (depends on 8)

The method for forming a semiconductor device of claim 8, further comprising:
forming a barrier layer over the gate dielectric layer before the gate electrode layer is formed;
recessing the gate electrode layer and the barrier layer to form a gate structure; and
forming a dielectric cap layer over the gate structure.

### Claim 10 (depends on 8)

The method for forming a semiconductor device of claim 8, wherein forming the gate electrode layer further comprises:
depositing a second gate electrode material over the remaining portion of the first gate electrode material.

### Claim 11 (depends on 10)

The method for forming a semiconductor device of claim 10, wherein a second gap is surrounded by the second gate electrode material.

### Claim 12 (depends on 11)

The method for forming a semiconductor device of claim 11, wherein a first distance between a bottommost surface of the first gap and the top surface of the semiconductor substrate is greater than a second distance between a bottommost surface of the second gap and the top surface of the semiconductor substrate.

### Claim 13 (depends on 11)

The method for forming a semiconductor device of claim 11, wherein forming the gate electrode layer further comprises:
etching the second gate electrode material to widen the second gap such that a second opening is surrounded by a remaining portion of the second gate electrode material, wherein a top width of the second opening is greater than a top width of the second gap.

### Claim 14 (depends on 13)

The method for forming a semiconductor device of claim 13, wherein forming the gate electrode layer further comprises:
depositing a third gate electrode material over the remaining portion of the second gate electrode material, wherein the first gate electrode material, the second gate electrode material and the third gate electrode material are made of tungsten.

### Claim 15

A method for forming a semiconductor device, comprising:
forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate;
forming a gate dielectric layer lining the trench; and
forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, wherein forming the gate electrode layer comprises:
depositing a first gate electrode material in the trench and over the gate dielectric layer and the top surface of the semiconductor substrate, wherein a first gap is surrounded by the first gate electrode material, wherein the gate electrode material in the trench includes top portions close to the top surface of the semiconductor and bottom portions away from the top surface of the semiconductor, wherein a thickness of the top portions is greater than a thickness of the bottom portions;
etching the first gate electrode material to reduce a thickness of the first gate electrode material in the trench and over the top surface of the semiconductor substrate; and
depositing a second gate electrode material over a remaining portion of the first gate electrode material after the first gate electrode material is etched.

### Claim 16 (depends on 15)

The method for forming a semiconductor device of claim 15, wherein the first gap is enlarged during the etching of the first gate electrode material such that a first opening is surrounded by the remaining portion of the first gate electrode material before the second gate electrode material is deposited, and a top width of the first opening is greater than a top width of the first gap.

### Claim 17 (depends on 15)

The method for forming a semiconductor device of claim 15, wherein forming the gate electrode layer further comprises
etching the second gate electrode material to reduce a thickness of the second gate electrode material over the top surface of the semiconductor substrate.

### Claim 18 (depends on 17)

The method for forming a semiconductor device of claim 17, wherein a second gap surrounded by the second gate electrode material is enlarged during the etching of the second gate electrode material such that a second opening is surrounded by a remaining portion of the second gate electrode material.

### Claim 19 (depends on 15)

The method for forming a semiconductor device of claim 15, wherein the first gate electrode material and the second gate electrode material include tungsten, and an etchant used to etch the first gate electrode material includes N2.

### Claim 20 (depends on 15)

The method for forming a semiconductor device of claim 15, further comprising:
etching the gate electrode layer to form a recess in the trench; and
forming a dielectric cap layer in the recess and over the top surface of the semiconductor substrate such that a portion of the dielectric cap layer is surrounded by the gate dielectric layer.