# US 11,309,192 B2 · Integrated circuit package supports > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,192 B2 - Document ID: US11309192B2 - Status: Granted - Kind: B2 - Application number: 16/000,205 - Filed: 2018-06-05 - Published: 2019-12-05 - Granted: 2022-04-19 - Earliest claimed: 2018-06-05 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Kristof Kuwawi Darmawikarta; Robert May; Sri Ranga Sai Boyapati; Srinivas V. Pietambaram; Chung Kwang Christopher Tan; Aleksandar Aleksov - Web page: https://patentgrep.com/patent/US11309192B2 ## CPC - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed. ## Claims ### Claim 1 An electronic apparatus, comprising: an integrated circuit (IC) package support, including: a first dielectric material, a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees, a second dielectric material on the first dielectric material, wherein the second dielectric material is non-photoimageable, and a second conductive via in the second dielectric material, wherein the second conductive via has tapered sidewalls with an angle that is greater than 80 degrees. ### Claim 2 (depends on 1) The electronic apparatus of claim 1, wherein the second conductive via has a diameter that is less than 20 microns. ### Claim 3 (depends on 1) The IC package support of claim 1, wherein the IC package support further includes: an adhesion promoter material on sidewalls of the second conductive via. ### Claim 4 (depends on 2) The electronic apparatus of claim 2, wherein the second conductive via has a diameter between 2 microns and 15 microns. ### Claim 5 (depends on 1) The electronic apparatus of claim 1, wherein the first dielectric material or the second dielectric material includes silica filler particles. ### Claim 6 (depends on 1) The electronic apparatus of claim 1, wherein the IC package support is a package substrate. ### Claim 7 (depends on 1) The electronic apparatus of claim 1, wherein the IC package support is an interposer. ### Claim 8 An electronic apparatus, comprising: an integrated circuit (IC) package support, including: a first dielectric material having a planar top surface, wherein the first dielectric material includes first filler particles having a first particle size, a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees, a second dielectric material on the top surface of the first dielectric material, wherein the second dielectric material includes second filler particles having a second particle size, and the second particle size is smaller than the first particle size, and a second conductive via in the second dielectric material, wherein the second conductive via has tapered sidewalls with an angle that is greater than 80 degrees. ### Claim 9 (depends on 8) The electronic apparatus of claim 8, wherein the IC package support further includes: a conductive pad in the second dielectric material, wherein the second conductive via is in electrical contact with the conductive pad. ### Claim 10 (depends on 9) The electronic apparatus of claim 9, wherein the conductive pad is between the first conductive via and the second conductive via, and the IC package support includes titanium on the sidewalls of the second conductive via and on sidewalls of the conductive pad. ### Claim 11 (depends on 10) The electronic apparatus of claim 10, wherein the second conductive via has tapered sidewalls with an angle that is greater than 85 degrees. ### Claim 12 (depends on 8) The electronic apparatus of claim 8, wherein a diameter of the second conductive via is less than 20 microns. ### Claim 13 (depends on 12) The electronic apparatus of claim 12, wherein a diameter of the second conductive via is between 2 microns and 15 microns. ### Claim 14 (depends on 8) The electronic apparatus of claim 8, wherein the second dielectric material has a loss tangent less than 0.005. ### Claim 15 An electronic apparatus, comprising: an integrated circuit (IC) package support, including: a first dielectric material having a planar top surface, a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees, a second dielectric material on the top surface of the first dielectric material, and a second conductive via in the second dielectric material, wherein the second conductive via has tapered sidewalls with an angle that is greater than 80 degrees. ### Claim 16 (depends on 15) The electronic apparatus of claim 15, wherein the second dielectric material is non-photoimageable. ### Claim 17 (depends on 15) The electronic apparatus of claim 15, wherein the second conductive via has a diameter between 2 microns and 15 microns. ### Claim 18 (depends on 15) The electronic apparatus of claim 15, wherein the first dielectric material or the second dielectric material includes silica filler particles. ### Claim 19 (depends on 15) The electronic apparatus of claim 15, further comprising: a die coupled to the IC package support. ### Claim 20 (depends on 15) The electronic apparatus of claim 15, wherein the IC package support is included in an IC package, the electronic apparatus further includes a circuit board, and the IC package is coupled to the circuit board. ### Claim 21 An electronic apparatus, comprising: an integrated circuit (IC) package support, including: a first dielectric material, a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees, a second dielectric material on the first dielectric material, a conductive pad in the second dielectric material, a second conductive via in the second dielectric material and in electrical contact with the conductive pad, wherein the second conductive via has tapered sidewalls with an angle that is greater than 80 degrees, and an adhesion promoter material on the sidewalls of the second conductive via and on sidewalls of the conductive pad, wherein the adhesion promoter material is not between the second conductive via and the conductive pad. ### Claim 22 (depends on 21) The electronic apparatus of claim 21, wherein the adhesion promoter material includes nitrogen or oxygen. ### Claim 23 (depends on 22) The electronic apparatus of claim 22, wherein the adhesion promoter material includes silicon. ### Claim 24 (depends on 21) The electronic apparatus of claim 21, wherein the electronic apparatus is a server device. ### Claim 25 (depends on 21) The electronic apparatus of claim 21, wherein the electronic apparatus is a handheld computing device.