# US 11,309,190 B2 · Semiconductor device and method of manufacture

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- Number: US 11,309,190 B2
- Document ID: US11309190B2
- Status: Granted
- Kind: B2
- Application number: 16/746,239
- Filed: 2020-01-17
- Published: 2021-07-22
- Granted: 2022-04-19
- Earliest claimed: 2020-01-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jian-Jou Lian; Chun-Neng Lin; Chieh-Wei Chen; Tzu-Ang Chiang; Ming-Hsi Yeh
- Web page: https://patentgrep.com/patent/US11309190B2

## CPC

- H10P 50/667: {by liquid etching only}
- C09K 13/00: Etching, surface-brightening or pickling compositions (for glass C03C15/00, {C03C25/66; for mortars, concrete, artificial or natural stone or ceramics C04B41/5338}; for metallic material C23F, C23G1/00, C25F1/00; {for semi-conductors H10P52/40})
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/0132: {the conductor being a metallic silicide}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/853: {comprising FinFETs}
- C09K 13/06: with organic material
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 76/2043: {using an anti-reflective coating}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C09K: MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a p-metal work function layer over a dielectric layer; and
applying a wet etching solution to the p-metal work function layer to remove a portion of the p-metal work function layer, wherein applying the wet etching solution forms a protective layer on an exposed surface of the dielectric layer after the portion of the p-metal work function layer has been removed, the wet etching solution comprising:
a metal etchant;
an inhibitor for the dielectric layer; and
a solvent.

### Claim 2 (depends on 1)

The method of claim 1, wherein the dielectric layer is hafnium oxide.

### Claim 3 (depends on 1)

The method of claim 1, wherein the inhibitor is a phosphoric acid.

### Claim 4 (depends on 1)

The method of claim 1, wherein the inhibitor is a carboxylic acid.

### Claim 5 (depends on 1)

The method of claim 1, wherein the inhibitor is an amino acid.

### Claim 6 (depends on 1)

The method of claim 1, wherein the inhibitor comprises a hydroxyl group.

### Claim 7 (depends on 1)

The method of claim 1, further comprising removing the protective layer.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
depositing a first p-work function layer onto a high-k dielectric layer; and
etching the first p-work function layer with a wet etching solution to expose a first portion of the high-k dielectric layer, wherein the wet etching solution comprises an inhibitor for the high-k dielectric layer, wherein the high-k dielectric layer reacts with the wet etching solution to form a protective layer on the high-k dielectric layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the protective layer comprises phosphorous, nitrogen, or carbon.

### Claim 10 (depends on 8)

The method of claim 8, wherein the wet etching solution further comprises:
a solvent;
a first metal etchant; and
an oxidizer.

### Claim 11 (depends on 8)

The method of claim 8, wherein the inhibitor comprises one or more of a phosphoric acid, a carboxylic acid, or an amino acid.

### Claim 12 (depends on 8)

The method of claim 8, wherein the protective layer forms a hydrophobic surface.

### Claim 13 (depends on 8)

The method of claim 8, wherein the high-k dielectric layer comprises hafnium oxide and the first p-work function layer comprises titanium nitride.

### Claim 14 (depends on 13)

The method of claim 13, wherein a selectivity of the wet etching solution between the titanium nitride and the high-k dielectric layer is at least 100:1.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
dispensing an etching solution over a p-metal work function material, the p-metal work function material being on a dielectric layer, wherein dispensing the etching solution etches the p-metal work function material to expose a portion of the dielectric layer, the etching solution forming a protective layer on the portion of the dielectric layer, the etching solution comprising:
a solvent;
a first metal etchant;
an oxidizer; and
an inhibitor comprising one or more of a phosphoric acid, a carboxylic acid, or an amino acid, the inhibitor being for the dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the inhibitor comprises di-(2-ethylhexyl)phosphoric acid.

### Claim 17 (depends on 15)

The method of claim 15, wherein the inhibitor comprises the carboxylic acid.

### Claim 18 (depends on 15)

The method of claim 15, wherein the inhibitor comprises glycine.

### Claim 19 (depends on 15)

The method of claim 15, wherein the inhibitor has a concentration of less than about 5%-volume.

### Claim 20 (depends on 15)

The method of claim 15, wherein the etching solution has a selectivity between titanium nitride and hafnium oxide of at least 100.