# US 11,309,189 B2 · Fin field effect transistor (FinFET) device structure and method for forming the same

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- Number: US 11,309,189 B2
- Document ID: US11309189B2
- Status: Granted
- Kind: B2
- Application number: 16/947,396
- Filed: 2020-07-30
- Published: 2020-11-12
- Granted: 2022-04-19
- Earliest claimed: 2015-07-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chang-Yin Chen; Chai-Wei Chang; Chia-Yang Liao; Bo-Feng Young
- Web page: https://patentgrep.com/patent/US11309189B2

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/283: {by chemical means}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.

## Claims

### Claim 1

A semiconductor device comprising:
a fin structure extending away from an isolation region over a semiconductor substrate, the fin structure comprising a top surface facing away from the semiconductor substrate;
a gate stack comprising:
a vertical upper portion above the top surface; and
a notched lower portion below the top surface, the vertical upper portion having a first width that is greater than a second width of the notched lower portion, the notched lower portion also having a third width that is less than the second width, an interface between the vertical upper portion and the notched lower portion being substantially level with the top surface of the fin structure;
spacers adjacent to the gate stack; and
an interlayer dielectric adjacent to the gate stack.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the vertical upper portion has a first height, wherein the notched lower portion has a second height, and wherein the first height is larger than the second height.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second width is greater than the third width by no more than about 15 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the notched lower portion has a trapezoidal shape.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein at least one of the spacers extends between the vertical upper portion and the semiconductor substrate.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the vertical upper portion has a surface facing the semiconductor substrate, the surface being in physical contact with a shallow trench isolation structure.

### Claim 7

A semiconductor device comprising:
a semiconductor fin;
a gate structure over the semiconductor fin, the gate structure having a first width located a first distance away from a semiconductor substrate, a second width located a second distance away from the semiconductor substrate, and a third width located a third distance away from the semiconductor substrate, the second distance being greater than the first distance and the second width being less than the first width, the third distance being greater than the second distance and the third width being greater than the second width, the gate structure having a sloped sidewall located between the first distance away from the semiconductor substrate and the second distance away from the semiconductor substrate, a top vertex of the sloped sidewall being substantially level with a top surface of the semiconductor fin; and
dielectric materials around the gate structure.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the gate structure has a vertical sidewall located between the second distance away from the semiconductor substrate and the third distance away from the semiconductor substrate.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the gate structure has a vertical upper portion at the third distance away from the semiconductor substrate, the vertical upper portion having a rectangular cross-section.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the gate structure has a notched lower portion at the first distance away from the semiconductor substrate and the second distance away from the semiconductor substrate, the notched lower portion having a trapezoidal cross-section.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the vertical upper portion has a first height, the notched lower portion has a second height different from the first height.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first height is larger than the second height.

### Claim 13

A semiconductor device comprising:
a spacer adjacent to a gate structure over a semiconductor fin, wherein the spacer comprises a first vertical portion, a first angled portion, and a first horizontal portion extending between the first vertical portion and the first angled portion, an interface between the first horizontal portion and the first angled portion being substantially level with a top surface of the semiconductor fin, the gate structure having a first width located a first distance away from a semiconductor substrate, a second width located a second distance away from the semiconductor substrate, and a third width located a third distance away from the semiconductor substrate, the second distance being greater than the first distance and the second width being less than the first width, the third distance being greater than the second distance and the third width being greater than the second width; and
an interlayer dielectric around the spacer and the gate structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the gate structure has a vertical upper portion at the third distance away from the semiconductor substrate, the vertical upper portion having a rectangular cross-section.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the gate structure has a notched lower portion at the first distance away from the semiconductor substrate and the second distance away from the semiconductor substrate, the notched lower portion having a trapezoidal cross-section.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the vertical upper portion has a first height, the notched lower portion has a second height different from the first height.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the first height is larger than the second height.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, wherein a difference between the first width and the second width is in a range from about 0 nm to about 15 nm.

### Claim 19 (depends on 1)

The semiconductor device of claim 1, wherein the top surface of the fin structure is parallel to a top surface of the isolation region.

### Claim 20 (depends on 13)

The semiconductor device of claim 13, further comprising a source/drain structure adjacent to the first vertical portion of the spacer.