# US 11,309,187 B2 · Methods of forming silicide contact in field-effect transistors

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- Number: US 11,309,187 B2
- Document ID: US11309187B2
- Status: Granted
- Kind: B2
- Application number: 17/102,213
- Filed: 2020-11-23
- Published: 2021-03-11
- Granted: 2022-04-19
- Earliest claimed: 2018-10-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Hsiung Lin; Shih-Cheng Chen; Chih-Hao Wang; Jung-Hung Chang; Jui-Chien Huang
- Web page: https://patentgrep.com/patent/US11309187B2

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0196: {by modifying properties of the inner spacers}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/509: {characterised by the material of the inner spacers}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a semiconductor fin disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the epitaxial S/D feature, the silicide layer is disposed on sidewalls of the epitaxial S/D feature, a dielectric layer disposed over sidewalls of the silicide layer, and an S/D contact disposed over the epitaxial S/D feature in an interlayer dielectric (ILD) layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor fin disposed over a substrate;
an epitaxial source/drain (S/D) feature disposed over the semiconductor fin;
a silicide layer disposed over the epitaxial S/D feature, wherein the silicide layer is disposed on sidewalls of the epitaxial S/D feature;
a dielectric layer disposed over sidewalls of the silicide layer; and
an S/D contact disposed over the epitaxial S/D feature in an interlayer dielectric (ILD) layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer is a first dielectric layer, further comprising a second dielectric layer, wherein the second dielectric layer is disposed along sidewalls of the silicide layer and separates the silicide layer from the first dielectric layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising an air gap between a bottom portion of the epitaxial S/D feature and the bottom portion of the dielectric layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a bottom surface of the epitaxial S/D feature contacts a top surface of the semiconductor fin.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor fin includes a stack of semiconductor layers, the semiconductor structure further comprising a metal gate structure disposed over the substrate and adjacent to the epitaxial S/D feature, wherein the metal gate structure includes a top portion disposed over the semiconductor fin and a bottom portion interleaved with the stack of semiconductor layers.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, further comprising a dielectric fin disposed adjacent and parallel to the semiconductor fin and over the substrate, wherein the dielectric layer is disposed on sidewalls of the dielectric fin.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein a thickness of the silicide layer is at least about 30% of a separation distance between a sidewall of the epitaxial S/D feature and one of the sidewalls of the dielectric fin.

### Claim 8

A semiconductor structure, comprising:
a fin including a stack of semiconductor layers disposed over a substrate;
an epitaxial source/drain (S/D) feature disposed over a portion of the fin;
a silicide layer wrapped around sidewalls of the epitaxial S/D feature;
a gate structure disposed over the substrate, wherein the gate structure includes a top portion disposed over the fin and a bottom portion interleaved with the stack of semiconductor layers; and
an S/D contact disposed adjacent to the gate structure, wherein the S/D contact contacts the silicide layer.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, further comprising an inner spacer separating the bottom portion of the gate structure from the epitaxial S/D feature.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising an air gap disposed between the inner spacer and the epitaxial S/D feature.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8, further comprising a dielectric layer disposed along sidewalls of the silicide layer and a contact etch-stop layer (CESL) disposed on the dielectric layer.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein a bottom portion of the dielectric layer is disposed between a bottom surface of the CESL and the substrate.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11, further comprising an air gap disposed between a bottom portion of the epitaxial S/D feature and a bottom portion of the dielectric layer.

### Claim 14 (depends on 8)

The semiconductor structure of claim 8, further comprising a contact etch-stop layer (CESL) disposed over sidewalls of the silicide layer and an air gap disposed between a bottom portion of the epitaxial S/D feature and a bottom portion of the CESL.

### Claim 15

A semiconductor structure, comprising:
a semiconductor fin protruding from a substrate;
isolation features disposed over the substrate and surrounding a bottom portion of the semiconductor fin;
an epitaxial source/drain (S/D) feature disposed over the semiconductor fin;
a silicide layer wrapping around the epitaxial S/D feature;
a contact etch-stop layer (CESL) disposed over the silicide layer;
an interlayer dielectric (ILD) layer disposed over the CESL; and
an S/D contact embedded in the ILD layer, wherein the S/D contact contacts the silicide layer.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, further comprising a dielectric layer disposed over sidewalls of the CESL.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein a bottom portion of the dielectric layer is disposed between the CESL and the isolation features, and wherein an air gap separates the bottom portion of the dielectric layer and the epitaxial S/D feature.

### Claim 18 (depends on 15)

The semiconductor structure of claim 15, further comprising an air gap disposed between a bottom portion of the epitaxial S/D feature and a bottom portion of the CESL.

### Claim 19 (depends on 15)

The semiconductor structure of claim 15, further comprising a dielectric fin oriented parallel to the semiconductor fin, wherein a bottom portion of the dielectric fin is disposed in the isolation features.

### Claim 20 (depends on 15)

The semiconductor structure of claim 15, wherein the semiconductor fin includes a stack of semiconductor layers, the semiconductor structure further comprising a metal gate structure disposed over the substrate and adjacent to the epitaxial S/D feature, wherein the metal gate structure includes a top portion disposed over the semiconductor fin and a bottom portion interleaved with the stack of semiconductor layers.