# US 11,309,185 B2 · Fin field-effect transistor and method of forming the same

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- Number: US 11,309,185 B2
- Document ID: US11309185B2
- Status: Granted
- Kind: B2
- Application number: 16/859,538
- Filed: 2020-04-27
- Published: 2021-10-28
- Granted: 2022-04-19
- Earliest claimed: 2020-04-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Tzu Ang Chiang; Ming-Hsi Yeh; Chun-Neng Lin; Jian-Jou Lian; Po-Yuan Wang; Chieh-Wei Chen
- Web page: https://patentgrep.com/patent/US11309185B2

## CPC

- H10D 64/01328: {by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 50/283: {by chemical means}
- H10P 50/667: {by liquid etching only}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a gate trench over a semiconductor fin, the gate trench including an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers;
forming a metal gate in the lower portion of the gate trench, wherein the metal gate is disposed over a first portion of a gate dielectric layer;
depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer; and
removing the second portion of the gate dielectric layer, while leaving the gate electrode substantially intact.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming a gate trench over a semiconductor fin comprises removing a dummy gate structure straddling a central portion of the semiconductor fin.

### Claim 3 (depends on 1)

The method of claim 1, wherein the metal material comprises tungsten.

### Claim 4 (depends on 1)

The method of claim 1, wherein removing the second portion of the gate dielectric layer comprises etching the second portion of the gate dielectric layer with a wet etching solution, and the wet etching solution etches a material of the gate dielectric layer at a faster rate than the metal material.

### Claim 5 (depends on 4)

The method of claim 4, wherein the wet etching solution comprises an etchant, an oxidant, and a stabilizer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the etchant is a fluoride-based acid, the oxidant is a perchloric acid, and the stabilizer is an ethylenediaminetetraacetic acid.

### Claim 7 (depends on 6)

The method of claim 6, wherein the etchant has a concentration within a solvent of between about 0.5% and about 15%, the oxidant has a concentration within the solvent of between about 3% and about 20%, and the stabilizer has a concentration within the solvent of between about 0.1% and about 5%.

### Claim 8 (depends on 1)

The method of claim 1, wherein the gate dielectric layer comprises one or more high-k dielectric materials.

### Claim 9 (depends on 1)

The method of claim 1, wherein the metal gate further comprises:
one or more work function layers;
an optional capping layer; and
a glue layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming a metal gate in the lower portion of the gate trench comprises:
removing a portion of the glue layer in the upper portion of the gate trench;
removing a portion of the optional capping layer in the upper portion of the gate trench; and
removing a portion of the one or more work function layers in the upper portion of the gate trench.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
removing a dummy gate structure that overlays a portion of a semiconductor fin;
forming a metal gate over the portion of the semiconductor fin, wherein the metal gate is disposed over a first portion of a gate dielectric layer;
depositing a metal material to form a gate electrode contacting the metal gate, while exposing a second portion of the gate dielectric layer; and
etching the second portion of the gate dielectric layer with the gate electrode exposed during the etching, wherein the gate electrode remains substantially intact.

### Claim 12 (depends on 11)

The method of claim 11, wherein the metal material comprises tungsten, and the gate dielectric layer comprises at least one high-k dielectric material.

### Claim 13 (depends on 11)

The method of claim 11, wherein etching the second portion of the gate dielectric layer comprises exposing the second portion of the gate dielectric layer and the gate electrode to a wet etching solution, the wet etching solution configured to etch a material of the gate dielectric layer at a faster rate than the metal material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the wet etching solution comprises an etchant, an oxidant, and a stabilizer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the etchant is a fluoride-based acid, the oxidant is a perchloric acid, and the stabilizer is an ethylenediaminetetraacetic acid.

### Claim 16 (depends on 15)

The method of claim 15, wherein the etchant has a concentration within a solvent of between about 0.5% and about 15%, the oxidant has a concentration within the solvent of between about 3% and about 20%, and the stabilizer has a concentration within the solvent of between about 0.1% and about 5%.

### Claim 17 (depends on 11)

The method of claim 11, wherein the metal gate further comprises:
one or more work function layers;
an optional capping layer; and
a glue layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming a metal gate in the lower portion of the gate trench comprises:
removing a portion of the glue layer in the upper portion of the gate trench;
removing a portion of the optional capping layer in the upper portion of the gate trench; and
removing a portion of the one or more work function layers in the upper portion of the gate trench.

### Claim 19

A method of manufacturing a semiconductor device, comprising:
forming a metal gate straddling a semiconductor fin, wherein the metal gate comprises a gate dielectric layer and at least one work function layer, and wherein the at least one work function layer overlays a lower portion of the gate dielectric layer with an upper portion of the gate dielectric layer extended above the at least one work function layer;
depositing a metal material to form a gate electrode contacting the metal gate, while leaving the second portion of the gate dielectric layer exposed; and
etching the second portion of the gate dielectric layer while leaving the gate electrode substantially intact.

### Claim 20 (depends on 19)

The method of claim 19, wherein the metal material comprises tungsten, and the gate dielectric layer comprises at least one high-k dielectric material.