# US 11,309,055 B2 · Power loss test engine device and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,055 B2 - Document ID: US11309055B2 - Status: Granted - Kind: B2 - Application number: 16/227,021 - Filed: 2018-12-20 - Published: 2020-06-25 - Granted: 2022-04-19 - Earliest claimed: 2018-12-20 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Claudio Giaccio; Ferdinando Pascale; Raffaele Mastrangelo; Erminio Di Martino; Ferdinando D'Alessandro; Cristiano Castellano; Andrea Castaldo - Web page: https://patentgrep.com/patent/US11309055B2 ## CPC - G11C 5/143: {Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence)} - G11C 29/50: Marginal testing, e.g. race, voltage or current testing - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters - G11C 29/021: {in voltage or current generators} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event. ## Claims ### Claim 1 A test system, comprising: a power management device configured to selectively trigger a power loss event in a memory device under test; a host device, including a host driver, wherein the host device is coupled to the power management device; and power loss logic in the host device to determine when one or more test conditions have been met in a memory operation between the host device and the memory device under test, and instruct the power management device to trigger the power loss event as determined by the one or more test conditions, wherein the test conditions in the power loss logic include recognition of an external trigger to cause the power management device to initiate a power loss to the memory device under test, the external trigger originating outside the power loss logic. ### Claim 2 (depends on 1) The test system of claim 1, wherein the memory device is a Unified Flash Specification (UFS) memory device. ### Claim 3 (depends on 1) The test system of claim 1, further including a recording system to track the one or more test conditions in the memory operation and to record whether or not a power loss event was triggered. ### Claim 4 (depends on 1) The test system of claim 1, wherein the test conditions in the power loss logic include recognition of a protocol event in transmission of a packet from the host device to the memory device under test. ### Claim 5 (depends on 1) The test system of claim 1, wherein the test conditions in the power loss logic include recognition of a protocol event in transmission of a packet from the memory device under test to the host device. ### Claim 6 (depends on 1) The test system of claim 1, wherein the test conditions in the power loss logic include recognition of a device management entity (DME) command. ### Claim 7 (depends on 1) The test system of claim 1, wherein the external trigger comes from the memory device under test. ### Claim 8 (depends on 1) The test system of claim 1, wherein the test conditions in the power loss logic include monitoring a counter of one or more events before trigger of the power loss event. ### Claim 9 (depends on 1) The test system of claim 1, wherein the test conditions in the power loss logic include monitoring a timer before trigger of the power loss event. ### Claim 10 A test system, comprising: a power management device configured to selectively trigger a power loss event in a memory device under test; a host device, including a host driver, wherein the host device is coupled to the power management device; power loss logic in the host device to determine when one or more test conditions have been met in a memory operation between the host device and the memory device under test, and instruct the power management device to trigger the power loss event as determined by the one or more test conditions, wherein the test conditions in the power loss logic include recognition of an external trigger to cause the power management device to initiate a power loss to the memory device under test, the external trigger originating outside the power loss logic; and a number of registers in the host device to track the one or more test conditions in the memory operation and whether or not a power loss event was triggered. ### Claim 11 (depends on 10) The test system of claim 10, wherein the registers include one or more registers chosen from a feature configuration register, a timer register, and a power loss register. ### Claim 12 (depends on 10) The test system of claim 10, wherein the memory device is a Unified Flash Specification (UFS) memory device. ### Claim 13 A method of testing a memory device, comprising: setting a test protocol in a host device, wherein the test protocol checks for one or more test conditions in a memory operation between the host device and a memory device under test; triggering a power loss in the memory device under test if selected test conditions have been met, wherein the test conditions in the power loss logic include recognition of an external trigger to cause the power management device to initiate a power loss to the memory device under test, the external trigger originating outside the power loss logic; and recording the one or more test conditions as they occur to make a record of a chain of events associated with triggering the power loss in the memory device under test. ### Claim 14 (depends on 13) The method of claim 13, wherein recording the one or more test conditions includes recording in one or more registers located in the host device. ### Claim 15 (depends on 13) The method of claim 13, wherein triggering a power loss in the memory device under test includes triggering a power loss in a Unified Flash Specification (UFS) memory device. ### Claim 16 (depends on 13) The method of claim 13, wherein triggering a power loss in the memory device under test, includes monitoring a counter of one or more events before trigger of the power loss event. ### Claim 17 (depends on 13) The method of claim 13, wherein triggering a power loss in the memory device under test includes monitoring a timer before trigger of the power loss event.