# US 11,309,053 B2 · Semiconductor memory device and storage device

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- Number: US 11,309,053 B2
- Document ID: US11309053B2
- Status: Granted
- Kind: B2
- Application number: 17/009,404
- Filed: 2020-09-01
- Published: 2021-03-18
- Granted: 2022-04-19
- Earliest claimed: 2019-09-13
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Takehisa Kurosawa; Koichi Shinohara; Yusuke Tanefusa
- Web page: https://patentgrep.com/patent/US11309053B2

## CPC

- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/14: Implementation of control logic, e.g. test mode decoders
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed.

## Claims

### Claim 1

A storage device comprising:
a first semiconductor memory device; and
a second semiconductor memory device; and
a memory controller configured to control the first semiconductor memory device and the second semiconductor memory device,
wherein the memory controller is configured to output reference data after issuing a predetermined command to the first semiconductor memory device and the second semiconductor memory device,
the first semiconductor memory device includes:
a first memory cell array including a plurality of memory cells;
a first processing circuit configured to write data into the first memory cell array;
a first timer configured to set a first waiting time;
a first command decoder configured to receive a command output from the memory controller; and
a first training circuit configured:
to wait until the first waiting time has passed since the predetermined command is received by the first command decoder, and
to perform a first process relating to determination of a correction value for a signal, which has been sent from the memory controller to the first processing circuit, based on the reference data after the first waiting time has passed,
wherein the second semiconductor memory device includes:
a second memory cell array including a plurality of memory cells;
a second processing circuit configured to write data into the second memory cell array;
a second timer configured to set a second waiting time;
a second command decoder configured to receive a command output from the memory controller; and
a second training circuit configured:
to wait until the second waiting time has passed since the predetermined command is received by the second command decoder, and
to perform a second process relating to the determination of a correction value for a signal, which has been sent from the memory controller to the second processing circuit, based on the reference data after the second waiting time has passed, and
the second waiting time is longer than the first waiting time.

### Claim 2 (depends on 1)

The storage device according to claim 1, wherein
the first semiconductor memory device further includes a first storage configured to store first information,
the first timer is configured to determine a length of the first waiting time based on the first information stored in the first storage,
the second semiconductor memory device further includes a second storage configured to store second information different from the first information, and
the second timer is configured to determine a length of the second waiting time based on the second information stored in the second storage.

### Claim 3 (depends on 1)

The storage device according to claim 1, wherein the first information is a first address set for the first semiconductor memory device, and the second information is a second address set for the second semiconductor memory device.

### Claim 4 (depends on 1)

The storage device according to claim 1, wherein the second waiting time is set to be longer than a period during which the first process is performed by the first training circuit.

### Claim 5 (depends on 1)

The storage device according to claim 1, wherein each of the first process and the second process includes a process relating to the determination of a correction value for at least one of a phase of the signal, a waveform shape of the signal, and a duty ratio of the signal.

### Claim 6 (depends on 1)

The storage device according to claim 1, further comprising a third semiconductor memory device configured to be controlled by the memory controller,
wherein the memory controller is configured to output the reference data after issuing the predetermined command to the first semiconductor memory device, the second semiconductor memory device, and the third semiconductor memory device,
the third semiconductor memory device includes:
a third memory cell array including a plurality of memory cells;
a third processing circuit configured to write data into the third memory cell array;
a third timer configured to set a third waiting time;
a third command decoder configured to receive a command output from the memory controller.

### Claim 7 (depends on 6)

The storage device according to claim 6, wherein the third waiting time is set to be longer than a total of a period during which the first process is performed by the first training circuit and a period during which the second process is performed by the second training circuit.

### Claim 8 (depends on 1)

The storage device according to claim 1, wherein the first semiconductor memory device is connected to the memory controller by a first signal line, and the second semiconductor memory device is connected to the memory controller by sharing at least a part of the first signal line.

### Claim 9 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a storage configured to store unique information,
wherein the first timer is configured to determine a length of the waiting time based on the unique information stored in the storage.

### Claim 10 (depends on 6)

The semiconductor memory device according to claim 6, further comprising:
a third training circuit configured
to wait until the third waiting time has passed since the predetermined command is received by the second command decoder, and
to perform a third process relating to the determination of a correction value for a signal, which has been sent from the memory controller to the third processing circuit, based on the reference data after the third waiting time has passed, and
the third waiting time is longer than the second waiting time.

### Claim 11 (depends on 6)

The semiconductor memory device according to claim 6, wherein the third waiting time is longer than the second waiting time.

### Claim 12 (depends on 6)

The storage device according to claim 6, wherein the third semiconductor memory device is connected to the memory controller by a first signal line, wherein the third semiconductor memory device is connected to the memory controller by sharing at least a part of the first signal line.