# US 11,309,050 B2 · Memory controller and memory system having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,050 B2 - Document ID: US11309050B2 - Status: Granted - Kind: B2 - Application number: 16/932,188 - Filed: 2020-07-17 - Published: 2020-11-05 - Granted: 2022-04-19 - Earliest claimed: 2018-01-26 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Dae Gon Cho - Web page: https://patentgrep.com/patent/US11309050B2 ## CPC - G11C 29/38: Response verification devices - G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters - G11C 29/36: Data generation devices, e.g. data inverters - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract There are provided a memory controller and a memory system having the same. A memory controller includes: an internal memory for storing error injection information for an error test operation and error test information that is a result of the error test operation; and a central processing unit for receiving first sector data from a host, and performing an error test operation on a memory device according to the error injection information, when the error injection information is included in the first sector data. ## Claims ### Claim 1 A memory system comprising: a memory device; and a memory controller including an internal memory and a central processing unit, wherein the central processing unit is configured to: perform an error test operation on the memory device, in response to receiving an error test request including error injection information from a host, output error test information that is a result of the error test operation to the host, and store the error test information in the memory device after the error test operation is performed. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the internal memory is configured to store the error test request and the error test information. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the central processing unit generates a program command, a read command or an erase command according to the error test request. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the central processing unit controls the memory device to perform the error test operation by transmitting at least one of a program command, a read command or an erase command. ### Claim 5 (depends on 1) The memory system of claim 1, wherein the central processing unit identifies the error injection information included in the error test request received. ### Claim 6 (depends on 1) The memory system of claim 1, wherein the error injection information includes at least one of: error type information including information on an error type; target block information including information on the memory device to perform the error test operation and addresses of a plane and a memory block included in the memory device; and target operation information including information on an operation internally performed without any request from the host. ### Claim 7 (depends on 6) The memory system of claim 6, wherein an internal operation includes at least one of a garbage collection operation, a wear leveling operation, or a read reclaim operation. ### Claim 8 (depends on 1) The memory system of claim 1, wherein the error test information includes at least one of: error injection result information including information on whether an error injection operation has been properly performed; test result information including information on whether subsequent processing of an error has been properly performed; and error address information including information on an address at which the error occurs. ### Claim 9 (depends on 1) The memory system of claim 1, wherein the central processing unit stores the error test information in the internal memory in response to the error test operation ending, and outputs sector data including the error test information to the host. ### Claim 10 (depends on 9) The memory system of claim 9, wherein the sector data is a transmission unit for outputting to the host. ### Claim 11 A memory system comprising: a memory device; and a memory controller configured to receive a first command set including error injection information and a second command set including memory operation information related to at least one of a read operation, an erase operation and a program operation on the memory device from a host, output error test information to the host, and store the error test information, wherein a central processing unit is configured to initiate a command to perform at least one of the read operation, the erase operation and the program operation based on the second command set at a memory block selected based on the error injection information. ### Claim 12 (depends on 11) The memory system of claim 11, wherein the memory controller determines whether the error injection information is included in the first command set. ### Claim 13 (depends on 11) The memory system of claim 11, wherein the memory controller receives the error injection information included in sector data which is one of first to nth sectors sequentially transmitted to the memory controller from the host. ### Claim 14 (depends on 11) The memory system of claim 11, wherein the memory controller receives the error injection information included in sector data whose size is a transmission unit between the memory system and the host. ### Claim 15 (depends on 11) The memory system of claim 11, wherein the memory controller performs an error test operation after the memory controller determines whether the error injection information is included in the first command set. ### Claim 16 (depends on 11) The memory system of claim 11, wherein the central processing unit controls the memory device to perform an error test operation by transmitting at least one of a program command, a read command or an erase command. ### Claim 17 (depends on 11) The memory system of claim 11, wherein the central processing unit identifies the error injection information included in the first command set. ### Claim 18 (depends on 11) The memory system of claim 11, wherein the error injection information includes at least one of: error type information including information on whether an error type is a read error type, a program error type or an erase error type; target block information including information on the memory device to perform an error test operation and addresses of a plane and a memory block included in the memory device; and target operation information including information on an operation internally performed without any request from the host. ### Claim 19 (depends on 11) The memory system of claim 11, wherein the error test information includes at least one of: error injection result information including information on whether an error injection operation has been properly performed; test result information including information on whether subsequent processing of an error has been properly performed; and error address information including information on an address at which the error occurs. ### Claim 20 (depends on 11) The memory system of claim 11, wherein the memory controller stores the error test information in an internal memory and the memory device.