# US 11,309,049 B2 · Direct memory access using JTAG cell addressing

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- Number: US 11,309,049 B2
- Document ID: US11309049B2
- Status: Granted
- Kind: B2
- Application number: 16/624,665
- Filed: 2019-05-31
- Published: 2021-10-28
- Granted: 2022-04-19
- Earliest claimed: 2019-05-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Alberto Troia; Antonino Mondello
- Web page: https://patentgrep.com/patent/US11309049B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 29/32: Serial access; Scan testing
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/106: {Data output latches}
- G11C 7/1087: {Data input latches}
- G11C 29/42: using error correcting codes [ECC] or parity check
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- G06F 2212/1024: Latency reduction
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G11C 2029/3202: {Scan chain}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access. A method for retrieving data from the memory component is also disclosed.

## Claims

### Claim 1

A memory device, couplable to a host device or a system-on-chip (SoC), comprising:
an array of memory cells with associated decoding and sensing circuitry, wherein a plurality of sub arrays of the array of memory cells is independently addressable inside the memory device;
sense amplifiers coupled to corresponding outputs of the plurality of sub-arrays and coupled to a communication channel of the host device or the SoC; and
a scan chain including modified Joint Test Action Group (JTAG) cells coupled in parallel between an output of the sense amplifiers and the communication channel, wherein the memory device is configured to fill the communication channel with an enlarged memory page including data, corresponding address bits, and ECC bits of each sub array of the plurality of sub arrays.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the modified JTAG cells include boundary-scan cells including a plurality of latches between a parallel input and parallel output.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the boundary scan cells include an input multiplexer and an output multiplexer and wherein the plurality of latches is coupled between the input multiplexer and the output multiplexer.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the plurality of latches is connected in a pipeline between a parallel input and a parallel output of each cell.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the modified JTAG cells are serially connected in the scan chain.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein each sub array of the plurality of sub arrays is structured in memory blocks including each at least 256 rows and each row includes at least sixteen pages comprising a memory word, corresponding address bits, and corresponding ECC bits.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the output of sense amplifiers is configured to combine data cells, address cells, and ECC cells.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the size of a memory page of each sub array includes at least 168 Bits.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the memory device is a flash memory device structurally independent from the host device or the SoC, wherein the memory device is couplable to the host device or the SoC through a plurality of interconnection pads, and wherein the communication channel is configured to perform read operation in a direct memory access.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the Direct Memory Access includes the modified JTAG cells and the sense amplifiers for addressing, directly, a location of the array of memory cells of the flash memory device.

### Claim 11 (depends on 9)

The memory device of claim 9, wherein the flash memory device is configured to apply the direct memory access for intra-chip data transfer in multi-core communication between the flash memory device and the host device or the SoC.

### Claim 12

An apparatus, comprising:
a system-on-chip (SoC) device;
a non-volatile memory device having a structurally independent structure from the SoC device;
an interconnection pin of the non-volatile memory device coupled to an interconnection pin of the SoC device;
a memory array in the memory device including a plurality of independently addressable sub arrays;
sense amplifiers coupled to corresponding outputs of the sub arrays and coupled to a communication channel of the SoC device; and
a scan chain comprising modified Joint Test Action Group (JTAG) cells coupled in parallel between an output of the sense amplifiers and the communication channel to perform read operations in a direct memory access, wherein the apparatus is configured to fill the communication channel with an enlarged memory page including data, corresponding address bits, and ECC bits of each sub array of the plurality of sub arrays.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein a sense amplifier of the sense amplifiers is configured to output data cells, address cells, and ECC cells.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein the modified JTAG cells include boundary-scan cells including a plurality of latches between a parallel input and parallel output.

### Claim 15 (depends on 12)

The apparatus of claim 12, wherein the modified JTAG cells are serially connected in the scan chain.

### Claim 16

An integrated circuit, comprising:
an array of memory cells including a plurality of independently addressable sub arrays;
sense amplifiers coupled to corresponding outputs of the sub arrays and coupled to a communication channel of a system-on-chip (SoC); and
a scan chain formed by modified Joint Test Action Group (JTAG) cells coupled in parallel between an output of the sense amplifiers and the communication channel to perform read operations in a direct memory access, wherein the integrated circuit is configured to fill the communication channel with an enlarged memory page including data, corresponding address bits, and ECC bits of each sub array of the plurality of sub arrays.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein said modified JTAG cells include boundary-scan cells including latches between a parallel input and parallel output.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the array of memory cells comprises data cells and corresponding address and ECC cells.