# US 11,309,044 B2 · Test circuit for testing a storage circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,044 B2 - Document ID: US11309044B2 - Status: Granted - Kind: B2 - Application number: 16/847,010 - Filed: 2020-04-13 - Published: 2021-10-14 - Granted: 2022-04-19 - Earliest claimed: 2020-04-13 - Assignees: Vanguard International Semiconductor Corporation - Applicants: Vanguard International Semiconductor Corporation - Inventors: Jian-Yuan Hsiao; Po-Yuan Tang; Wei-Ting Chen; Feng-Chih Kuo - Web page: https://patentgrep.com/patent/US11309044B2 ## CPC - G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation - G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)} - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G11C 29/1201: {comprising I/O circuitry} - G11C 29/14: Implementation of control logic, e.g. test mode decoders - G11C 29/20: using counters or linear-feedback shift registers [LFSR] - G11C 29/36: Data generation devices, e.g. data inverters - G11C 29/38: Response verification devices - G11C 29/46: Test trigger logic - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger - G11C 2029/1206: {Location of test circuitry on chip or wafer} - G11C 2029/1208: {Error catch memory} - G11C 2029/3602: {Pattern generator} - G11C: STATIC STORES (semiconductor memory devices H10B) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A test circuit testing a storage circuit and including a controller, a pattern-generator circuit, a comparing circuit, and a first register is provided. The storage circuit includes a storage block. The controller is configured to generate a plurality of internal test signals. The pattern-generator circuit generates and provides test data to the storage circuit according to the internal test signal. The storage circuit writes the test data into the storage block and reads the storage block to generate read data. The comparing circuit compares the test data and the read data to generate a test result. The first register stores the test result. The controller determines whether the storage circuit is working normally according to the test result stored in the first register. ## Claims ### Claim 1 A test circuit for testing a storage circuit which comprises a storage block, comprising: a test access circuit configured to receive a first access address, a first control command, external test data, and a mode selection signal; a controller configured to generate an address signal, a control signal, a data component; a pattern-generator circuit generating and providing test data to the storage circuit according to the data component or the external test data, wherein the storage circuit writes the external test data or the internal test data into the storage block and reads the storage block to generate read data; a comparing circuit comparing the test data and the read data to generate a test result; and a first register storing the test result, wherein the controller determines whether the storage circuit is working normally according to the test result stored in the first register, wherein: when a characteristic parameter of the mode selection signal meets a first predetermined condition, the test access circuit directs the controller to stop providing the address signal, the control signal, and the data component such that the pattern-generator circuit generates an access address, a control command, and the test data according to the first access address, the first control command, and the external test data and provides the access address, the control command, and the test data to the storage circuit, and when the characteristic parameter of the mode selection signal meets a second predetermined condition, the test access circuit directs the controller to provide the address signal, the control signal, and the data component so that the pattern-generator circuit generates the access address, the control command, and the test data according to the address signal, the control signal, and the data component and provides the access address, the control command, and the internal test data to the storage circuit. ### Claim 2 (depends on 1) The test circuit as claimed in claim 1, wherein the storage circuit is a static random access memory (SRAM). ### Claim 3 (depends on 1) The test circuit as claimed in claim 1, wherein the pattern-generator circuit comprises: a data generator generating internal test data according to the data component; a first selection circuit using the internal test data or the external test data as the test data according to a selection signal; an address generator generating a second access address according to the address signal; a second selection circuit outputting the first access address or the second access address to the storage circuit according to the selection signal; a control generator generating a second control command according to the control signal; and a third selection circuit outputting the first control command or the second control command to the storage circuit according to the selection signal. ### Claim 4 (depends on 1) The test circuit as claimed in claim 1, wherein the first register is a first D flip-flop, and the first D flip-flop receives the test result, uses the test result as a first output signal, and provides the first output signal to the controller according to an operation clock. ### Claim 5 (depends on 4) The test circuit as claimed in claim 4, wherein the controller comprises: a first combinational logic circuit receiving the first output signal, wherein in response to the first output signal indicating that the read data conforms with the test data, the first combinational logic circuit generates a state signal; a second D flip-flop receiving the state signal and using the state signal as a second output signal according to the operation clock; and a second combinational logic circuit generating the address signal, the control signal, and the data component according to the second output signal. ### Claim 6 (depends on 5) The test circuit as claimed in claim 5, wherein in response to the first D flip-flop outputting the first output signal, the second D flip-flop outputs the second output signal. ### Claim 7 (depends on 5) The test circuit as claimed in claim 5, wherein when the first D flip-flop provides the first output signal to the first combinational logic circuit, the second D flip-flop provides the second output signal to the second combinational logic circuit. ### Claim 8 (depends on 4) The test circuit as claimed in claim 4, wherein the controller comprises: a first combinational logic circuit determining whether the storage circuit is working normally according to the mode selection signal, the test result, and series data to generate a determination result and decoding the determination result into a plurality of state codes; a plurality of second D flip-flops receiving the state codes and the operation clock, wherein the second D flip-flops use the state codes as a plurality of output signals according to the operation clock; and a second combinational logic circuit generating the address signal, the control signal, the data component according to the output signals. ### Claim 9 (depends on 1) The test circuit as claimed in claim 1, further comprising: a second register configured to store the test result; and a logic gate coupled to the first register and the second register and generating an output signal according to the test result stored in the first register and the second register, wherein the controller determines whether the storage circuit is working normally according to the output signal. ### Claim 10 (depends on 9) The test circuit as claimed in claim 9, wherein the logic gate is an OR gate. ### Claim 11 An electronic device comprising: a storage circuit comprising a storage block; and a test circuit configured to test the storage circuit and comprising: a test access circuit configured to receive a first access address, a first control command, external test data, and a mode selection signal; a controller configured to generate an address signal, a control signal, a data component; a pattern-generator circuit generating and providing test data to the storage circuit according to the data component or the external test data, wherein the storage circuit writes the test data into the storage block and reads the storage block to generate read data; a comparing circuit comparing the test data and the read data to generate a test result; and a first register storing the test result, wherein the controller determines whether the storage circuit is working normally according to the test result stored in the first register, wherein: when a characteristic parameter of the mode selection signal meets a first predetermined condition, the test access circuit directs the controller to stop providing the address signal, the control signal, and the data component such that the pattern-generator circuit generates an access address, a control command, and the test data according to the first access address, the first control command, and the external test data and provides the access address, the control command, and the test data to the storage circuit, and when the characteristic parameter of the mode selection signal meets a second predetermined condition, the test access circuit directs the controller to provide the address signal, the control signal, and the data component so that the pattern-generator circuit generates the access address, the control command, and the test data according to the address signal, the control signal, and the data component and provides the access address, the control command, and the internal test data to the storage circuit. ### Claim 12 (depends on 11) The electronic device as claimed in claim 11, wherein the storage circuit is a static random access memory (SRAM). ### Claim 13 (depends on 11) The electronic device as claimed in claim 11, wherein the pattern-generator circuit comprises: a data generator generating internal test data according to the data component; a first selection circuit using the internal test data or the external test data of the external test signals as the test data according to a selection signal; an address generator generating a second access address according to the address signal; a second selection circuit outputting the first access address or the second access address to the storage circuit according to the selection signal; a control generator generating a second control command according to the control signal; and a third selection circuit outputting the first control command or the second control command to the storage circuit according to the selection signal. ### Claim 14 (depends on 11) The electronic device as claimed in claim 11, wherein the first register is a first D flip-flop, and the first D flip-flop receives the test result, uses the test result as a first output signal, and provides the first output signal to the controller according to an operation clock. ### Claim 15 (depends on 14) The electronic device as claimed in claim 14, wherein the controller comprises: a first combinational logic circuit receiving the first output signal, wherein in response to the first output signal indicating that the read data conforms with the test data, the first combinational logic circuit generates a state signal; a second D flip-flop receiving the state signal and using the state signal as a second output signal according to the operation clock; and a second combinational logic circuit generating the address signal, the control signal, and the data component according to the second output signal. ### Claim 16 (depends on 15) The electronic device as claimed in claim 15, wherein in response to the first D flip-flop outputting the first output signal, the second D flip-flop outputs the second output signal. ### Claim 17 (depends on 11) The electronic device as claimed in claim 11, further comprising: a second register configured to store the test result; and a logic gate coupled to the first register and the second register and generating an output signal according to the test result stored in the first register and the second register, wherein the controller determines whether the storage circuit is working normally according to the output signal. ### Claim 18 (depends on 17) The electronic device as claimed in claim 17, wherein the logic gate is an OR gate. ### Claim 19 (depends on 11) The electronic device as claimed in claim 11, wherein: the test access circuit is coupled to a test apparatus which is disposed independent of the electronic device, and when a characteristic parameter of the mode selection signal meets a third predetermined condition: the pattern-generator circuit generates the access address according to the address signal, generates the control command according to the control signal, and generates the test data according to the external test data, and the pattern-generator circuit provides the access address, the control command, and the test data to the storage circuit. ### Claim 20 (depends on 19) The electronic device as claimed in claim 19, wherein the test apparatus utilizes a wireless method to provide first access address, the first control command, and the external test data to the test access circuit.