# US 11,309,042 B2 · Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,042 B2 - Document ID: US11309042B2 - Status: Granted - Kind: B2 - Application number: 16/915,289 - Filed: 2020-06-29 - Published: 2021-12-30 - Granted: 2022-04-19 - Earliest claimed: 2020-06-29 - Assignees: Silicon Storage Technology, Inc. - Applicants: Silicon Storage Technology, Inc. - Inventors: Viktor Markov; Alexander Kotov - Web page: https://patentgrep.com/patent/US11309042B2 ## CPC - G11C 16/12: Programming voltage switching circuits - G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells} - G11C 7/02: with means for avoiding parasitic signals - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/10: Programming or data input circuits - G11C 16/107: {Programming all cells in an array, sector or block to the same state prior to flash erasing} - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 16/0425: {comprising cells containing a merged floating gate and select transistor} - G11C 2216/04: Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current. ## Claims ### Claim 1 A memory device, comprising: a plurality of non-volatile memory cells each comprising a first gate; and a controller configured to program one non-volatile memory cell of the plurality of non-volatile memory cells by: programming the one non-volatile memory cell to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a first read current, and subjecting the one non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current; wherein the controller is configured to perform the programming of the one non-volatile memory cell to the initial program state by: applying at least one first pulse of programming voltages to the one non-volatile memory cell, reading the one non-volatile memory cell using a read voltage applied to the first gate of the one non-volatile memory cell that is equal to the target threshold voltage to generate a second read current, and applying at least one second pulse of programming voltages to the one non-volatile memory cell in response to determining that the second read current is greater than the target read current. ### Claim 2 (depends on 1) The device of claim 1, wherein each of the plurality of non-volatile memory cells further comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between; a floating gate disposed vertically over and insulated from a first portion of the channel region; and a select gate disposed vertically over and insulated from a second portion of the channel region; wherein for each of the plurality of non-volatile memory cells, the first gate is disposed vertically over and insulated from the floating gate. ### Claim 3 (depends on 2) The device of claim 2, wherein each of the plurality of non-volatile memory cells further comprises: an erase gate disposed over and insulated from the source region. ### Claim 4 (depends on 1) The device of claim 1, wherein a voltage applied to the first gate as part of the second pulse of programming voltages is greater than a voltage applied to the first gate as part of the first pulse of programming voltages. ### Claim 5 (depends on 1) The device of claim 1, wherein the controller is further configured to: read the one non-volatile memory cell in a second read operation, in response to determining that the first read current is not greater than the target read current in the first read operation, using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a second read current, and subject the one non-volatile memory cell to additional programming in response to determining that the second read current is greater than the target read current. ### Claim 6 (depends on 5) The device of claim 5, wherein each of the plurality of non-volatile memory cells comprises a second gate, and wherein the controller is further configured to: apply a negative voltage to the second gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation; and apply a negative voltage to the second gate of the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation. ### Claim 7 (depends on 1) The device of claim 1, wherein each of the plurality of non-volatile memory cells comprises a second gate, and wherein the controller is further configured to apply a negative voltage to the second gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation. ### Claim 8 (depends on 1) The device of claim 1, wherein the controller is further configured to apply a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation. ### Claim 9 A memory device comprising: a plurality of non-volatile memory cells each comprising a first gate; and a controller configured to program one non-volatile memory cell of the plurality of non-volatile memory cells by: programming the one non-volatile memory cell to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a first read current, and subjecting the one non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current; wherein the controller is further configured to: read the one non-volatile memory cell in a second read operation, in response to determining that the first read current is not greater than the target read current in the first read operation, using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a second read current, and subject the one non-volatile memory cell to additional programming in response to determining that the second read current is greater than the target read current; wherein the controller is further configured to: apply a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation; and apply a negative voltage to the first gate of the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation. ### Claim 10 A method of programming one non-volatile memory cell of a plurality of non-volatile memory cells, wherein each of the plurality of non-volatile memory cells includes a first gate, the method comprising: programming the one non-volatile memory cell to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a first read current, and subjecting the one non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current; wherein the programming of the one non-volatile memory cell to the initial program state comprises: applying at least one first pulse of programming voltages to the one non-volatile memory cell; reading the one non-volatile memory cell using a read voltage applied to the first gate of the one non-volatile memory cell that is equal to the target threshold voltage to generate a second read current; and applying at least one second pulse of programming voltages to the one non-volatile memory cell in response to determining that the second read current is greater than the target read current. ### Claim 11 (depends on 10) The method of claim 10, wherein each of the plurality of non-volatile memory cells further comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between; a floating gate disposed vertically over and insulated from a first portion of the channel region; and a select gate disposed vertically over and insulated from a second portion of the channel region; wherein for each of the plurality of non-volatile memory cells, the first gate is disposed vertically over and insulated from the floating gate. ### Claim 12 (depends on 11) The method of claim 11, wherein each of the plurality of non-volatile memory cells further comprises: an erase gate disposed over and insulated from the source region. ### Claim 13 (depends on 10) The method of claim 10, wherein a voltage applied to the first gate as part of the second pulse of programming voltages is greater than a voltage applied to the first gate as part of the first pulse of programming voltages. ### Claim 14 (depends on 10) The method of claim 10, further comprising: reading the one non-volatile memory cell in a second read operation, in response to determining that the first read current is not greater than the target read current in the first read operation, using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a second read current, and subjecting the one non-volatile memory cell to additional programming in response to determining that the second read current is greater than the target read current. ### Claim 15 (depends on 14) The method of claim 14, wherein each of the plurality of non-volatile memory cells comprises a second gate, the method further comprising: applying a negative voltage to the second gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation; and applying a negative voltage to the second gate of the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation. ### Claim 16 (depends on 10) The method of claim 10, wherein each of the plurality of non-volatile memory cells comprises a second gate, the method further comprising: applying a negative voltage to the second gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation. ### Claim 17 (depends on 10) The method of claim 10, further comprising: applying a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation. ### Claim 18 A method of programming one non-volatile memory cell of a plurality of non-volatile memory cells, wherein each of the plurality of non-volatile memory cells includes a first gate, the method comprising: programming the one non-volatile memory cell to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a first read current, subjecting the one non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current, reading the one non-volatile memory cell in a second read operation, in response to determining that the first read current is not greater than the target read current in the first read operation, using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a second read current, subjecting the one non-volatile memory cell to additional programming in response to determining that the second read current is greater than the target read current, applying a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation, and applying a negative voltage to the first gate of the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.