# US 11,309,033 B2 · Memory device

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- Number: US 11,309,033 B2
- Document ID: US11309033B2
- Status: Granted
- Kind: B2
- Application number: 17/121,015
- Filed: 2020-12-14
- Published: 2021-10-28
- Granted: 2022-04-19
- Earliest claimed: 2020-12-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Taehyo Kim; Daeseok Byeon; Youngmin Jo; Seungwon Lee
- Web page: https://patentgrep.com/patent/US11309033B2

## CPC

- G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10W 90/00: Package configurations
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52)
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C 2211/5644: Multilevel memory comprising counting devices
- G11C 2211/5646: Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
- H10B 43/10: characterised by the top-view layout
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.

## Claims

### Claim 1

A memory device, comprising:
a memory area having a first memory block and a second memory block; and
a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable,
wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the second memory block stores security data that the control logic reads only in the second mode.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the control logic limits a control operation for the second memory block, when the number of accesses included in the scan data is equal to a predetermined reference number.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the control logic limits the control operation for the second memory block by authenticating a user using a password or biometric information.

### Claim 5 (depends on 3)

The memory device of claim 3, wherein the control logic limits the control operation for the second memory block by deleting data stored in a page buffer connected to the second memory block and changing a voltage level output by a voltage generator connected to the second memory block.

### Claim 6 (depends on 2)

The memory device of claim 2, wherein the control logic deletes data stored in the second memory block when an attempt to initialize the scan data is detected.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the control logic and the memory area are included in a single semiconductor chip.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the control logic is included in a first semiconductor chip and the memory area is included in a second semiconductor chip different from the first semiconductor chip.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the number of memory cells included in the first memory block is equal to the number of memory cells included in the second memory block, and
a data storage capacity of the first memory block is greater than a data storage capacity of the second memory block.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the control logic stores the scan data in flag cells which are included in the second memory block and are programmed in a single level cell (SLC) scheme.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the flag cells are connected to one word line in the second memory block.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein the control logic stores the scan data in at least one flag cell among memory cells included in the second memory block, and increases a threshold voltage of the at least one flag cell when the number of accesses is increased.

### Claim 13 (depends on 1)

The memory device of claim 1, further comprising:
first page buffers connected to the first memory block and executing a reading operation and a programming operation for the first memory block; and
second page buffers connected to the second memory block and executing a reading operation and a programming operation for the second memory block,
wherein the number of latches included in each of the first page buffers is different from the number of latches included in each of the second page buffers.

### Claim 14

A memory device, comprising:
a memory area having a plurality of memory blocks; and
a control logic configured to control the memory area,
wherein the control logic blocks access to at least one security block among the plurality of memory blocks in a first mode, and allows access to the at least one security block in a second mode, different from the first mode, and
when a reading operation for the at least one security block is executed in the first mode, the reading operation and a programming operation for the at least one security block are executed.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein in the programming operation for the security block, executed in the first mode, the control logic records scan data, wherein the scan data includes the number of reading operations for the security block executed in the first mode.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein the control logic initializes the security block when an attempt to initialize the scan data is detected.

### Claim 17 (depends on 14)

The memory device of claim 14, wherein the control logic executes an erase operation in a unit of each of the memory blocks when an erase command is received.

### Claim 18

A memory device, comprising:
first word lines stacked on a substrate;
first channel layers penetrating through the first word lines to extend in a first direction perpendicular to the substrate, and providing first memory cells accessible in a first mode and a second mode, different from the first mode;
second word lines stacked on the substrate and electrically separated from the first word lines;
second channel layers penetrating through the second word lines to extend in the first direction, and providing second memory cells accessible only in the second mode; and
a control logic configured to select one of the first mode and the second mode as an operation mode, and store data corresponding to the number of times the second memory cells are accessed in the first mode, in the second memory cells.

### Claim 19 (depends on 18)

The memory device of claim 18, further comprising:
a word line separating layer separating the first word lines and the second word lines.

### Claim 20 (depends on 18)

The memory device of claim 18, wherein the number of the first word lines is equal to the number of the second word lines, and the number of the first channel layers is equal to the number of the second channel layers; and
a data storage capacity of the first memory cells is different from a data storage capacity of the second memory cells.