# US 11,309,031 B2 · Periodic reduced word line bias which increases channel boosting

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- Number: US 11,309,031 B2
- Document ID: US11309031B2
- Status: Granted
- Kind: B2
- Application number: 17/008,926
- Filed: 2020-09-01
- Published: 2022-03-03
- Granted: 2022-04-19
- Earliest claimed: 2020-08-28
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Ming Wang; Liang Li; Peng Zhang; Yanli Zhang
- Web page: https://patentgrep.com/patent/US11309031B2

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated word lines to create periodic low points or dips in the channel boosting level. A normal pass voltage, Vpass, is applied to other unselected word lines. The low points create barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line. VpassL can be applied to designated word lines at the source and/or drain sides of the selected word line. A control circuit can be configured with various parameters for implementing the techniques.

## Claims

### Claim 1

An apparatus, comprising:
a control circuit configured to connect to a plurality of word lines, the plurality of word lines are connected to memory cells in a NAND string and comprise a selected word line and unselected word lines, and the NAND string comprises a channel; and
a memory interface connected to the control circuit, the control circuit is configured to issue a command via the memory interface to apply a plurality of voltage signals to the plurality of word lines to boost a voltage of the channel, the plurality of voltage signals comprise a program voltage signal applied to the selected word line, and voltage signals which increase from a respective initial voltage to a pass voltage, wherein among the unselected word lines, the pass voltage is lower for designated word lines spaced at intervals along the NAND string than for word lines between the designated word lines.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein:
the designated word lines are spaced at equal intervals along the NAND string; and
the equal intervals each comprise at least three word lines.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
among the designated word lines, a closest word line to the selected word line is N word lines away from the selected word line, and the intervals each comprise M word lines, where N≠M.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
among the designated word lines, a closest word line to the selected word line is N word lines away from the selected word line, and the intervals each comprise N word lines.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the designated word lines comprise unprogrammed word lines.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein:
the intervals are an increasing function of a distance of the selected word line from a first-programmed word line of the plurality of word lines.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein:
the pass voltage for the designated word lines is an increasing function of a distance of the selected word line from a first-programmed word line of the plurality of word lines.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein:
the pass voltage applied to the word lines between the designated word lines is no more than 2 V higher than the pass voltage applied to the designated word lines.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein:
the designated word lines are spaced at progressively larger intervals along the NAND string in a direction moving away from the selected word line.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein:
the pass voltage for the designated word lines is progressively higher for designated word lines which are progressively further from the selected word line.

### Claim 11

A method, comprising:
applying a program voltage signal to a selected word line in a program operation, the selected word line and unselected word lines are among a plurality of word lines connected to a selected NAND string and an unselected NAND string, and the unselected NAND string comprises a channel; and
during the applying of the program voltage signal, applying voltage signals to the unselected word lines, the voltage signals applied to the unselected word lines increase from respective initial voltages to respective pass voltages, creating periodic dips in boosting in the channel.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the periodic dips are adjacent to unselected word lines spaced apart along the unselected NAND string; and
the unselected word lines adjacent to the periodic dips are spaced apart from one another by at least two intervening word lines.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
the periodic dips are created in a portion of the unselected NAND string which is unprogrammed.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
the portion is a decreasing function of distance between the selected word line and a first programmed word line of the plurality of word lines.

### Claim 15 (depends on 13)

The method of claim 13, wherein:
the portion is on a drain side of the selected word line.

### Claim 16

An apparatus, comprising:
a NAND string comprising a plurality of memory cells and a channel; and
a plurality of word lines connected to the memory cells, each word line is adjacent to a respective region of the channel and is configured to carry a voltage signal which boosts a voltage of the respective region of the channel, the channel having a voltage with periodic dips along a length of the NAND string.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein:
the periodic dips occur over majority of the length of the NAND string.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein:
a voltage of word lines adjacent to regions of the channel having the periodic dips is a positive voltage and is no more than 2 V lower than a voltage of word lines adjacent to remaining regions of the channel.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein:
the periodic dips occur in respective regions of the channel which are adjacent to unselected word lines of the plurality of word lines while a program voltage is applied to a selected word line of the plurality of word lines.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein:
a voltage of word lines adjacent to regions of the channel having the periodic dips is a function of a position of the selected word line among the plurality of word lines.