# US 11,309,029 B2 · Semiconductor device and operating method thereof

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- Number: US 11,309,029 B2
- Document ID: US11309029B2
- Status: Granted
- Kind: B2
- Application number: 17/026,402
- Filed: 2020-09-21
- Published: 2021-01-07
- Granted: 2022-04-19
- Earliest claimed: 2018-12-19
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Han Soo Joo; Bong Yeol Park; Ji Hyun Seo; Hee Youl Lee
- Web page: https://patentgrep.com/patent/US11309029B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- H10B 41/30: characterised by the memory core region
- H10B 43/30: characterised by the memory core region
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.

## Claims

### Claim 1

A semiconductor device comprising:
a memory string coupled between a source line and a bit line, the memory string including at least one source select transistor, a plurality of memory cells, and at least one drain select transistor, wherein a channel region of the memory string includes a first channel region at one side of a selected memory cell among the plurality of memory cells and a second channel region at the other side of the selected memory cell; and
a control logic configured to boost the first channel region, apply a pre-program bias to a gate electrode of the selected memory cell such that electrons are injected into a space region of the selected memory cell, and apply a program bias to the gate electrode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein, after the memory string is coupled to the bit line, the first channel region is boosted by turning off the selected memory cell and applying a pass bias to gate electrodes of unselected memory cells among the plurality of memory cells.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the memory string is coupled to the bit line of a ground level.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein, when the selected memory cell is turned off, a negative bias is applied to a word line coupled to the selected memory cell.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein the pre-program bias is greater than the pass bias.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the pre-program bias is less than the program bias.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein, when the pre-program bias is applied, the pre-program bias is applied to at least one unselected memory cell adjacent to the selected memory cell among the unselected memory cells.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein, after the channel region is precharged, the first channel region is boosted.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first channel region is selectively boosted in the channel region.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the pre-program bias is applied after the first channel region is boosted.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the program bias is applied after the pre-program bias is applied.

### Claim 12

A semiconductor device comprising:
a memory string coupled between a source line and a bit line, the memory string including at least one first select transistor, a plurality of memory cells, and at least one second select transistor, wherein a channel region of the memory string includes a first channel region at one side of a selected memory cell among the plurality of memory cells and a second channel region at the other side of the selected memory cell; and
a control logic configured to couple the memory string to the source line or the bit line, turn off a selected memory cell, increase a level of word lines coupled to unselected memory cells among the plurality of memory cells to a pass bias such that the first channel region and the second channel region have different potential levels, increase a level of a word line coupled to the selected memory cell to a pre-program bias greater than the pass bias, and apply a program bias to the word line coupled to the selected memory cell.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the pre-program bias is applied after the first channel region is boosted.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the program bias is applied after the pre-program bias is applied.

### Claim 15

A semiconductor device comprising:
a source line;
a bit line;
a plurality of memory cells including a selected memory cell, a first group of unselected memory cells between the source line and the selected memory cell, and a second group of unselected memory cells between the selected memory cell and the bit line;
a first channel region including channel regions of the first group of unselected memory cells;
a second channel region including channel regions of the second group of unselected memory cells; and
a control logic suitable for:
boosting one of the first and second channel regions;
applying a pre-program bias to the selected memory cell; and
applying a program bias to the selected memory cell and a pass bias to the unselected memory cells, wherein the pre-program bias is less than the program bias and greater than the pass bias.