# US 11,309,028 B2 · Inference operation method and controlling circuit of 3D NAND artificial intelligence accelerator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,028 B2 - Document ID: US11309028B2 - Status: Granted - Kind: B2 - Application number: 17/011,039 - Filed: 2020-09-03 - Published: 2022-03-03 - Granted: 2022-04-19 - Earliest claimed: 2020-09-03 - Assignees: Macronix International Co., Ltd. - Applicants: Macronix International Co., Ltd. - Inventors: Po-Kai Hsu; Teng-Hao Yeh - Web page: https://patentgrep.com/patent/US11309028B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06N 5/04: Inference or reasoning models - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 11/54: using elements simulating biological cells, e.g. neuron - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F 2207/4824: Neural networks - G06N 20/00: Machine learning - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched. ## Claims ### Claim 1 An inference operation method of a 3D NAND artificial intelligence accelerator, wherein the 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line, a plurality of filter data bits are stored in the memory cells that are selected by the word lines, the string selecting lines and the bit lines when being read, a plurality of patterns are inputted to the bit lines for performing a Multiply-Accumulation (MAC) operation, and the inference operation method comprises: inputting the patterns to the bit lines; switching the word lines to switch the filter data bits; and switching the string selecting line groups to switch the filter data bits; wherein in a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched; wherein in the word line pioneering scheme and the string selecting line group pioneering scheme, when the patterns are switched, voltages of the word lines are held; and when the patterns are switched, voltages of the string selecting lines are held. ### Claim 2 (depends on 1) The inference operation method according to claim 1, wherein in the word line pioneering scheme and the string selecting line group pioneering scheme, one of the word lines is pre-charged before switching the patterns, and dis-charged after switching the patterns. ### Claim 3 (depends on 1) The inference operation method according to claim 1, wherein in the word line pioneering scheme, the word lines are switched before any one of the string selecting line groups is switched; and when the word lines are switched, voltages of the string selecting lines are held. ### Claim 4 (depends on 1) The inference operation method according to claim 1, wherein in the word line pioneering scheme, one of the string selecting line groups is pre-charged before switching the word lines, and dis-charged after switching the word lines; and when one of the string selecting line groups is switched, any one of the word lines is not switched. ### Claim 5 (depends on 1) The inference operation method according to claim 1, wherein in the string selecting line group pioneering scheme, one of the string selecting line groups is pre-charged before switching the patterns, and dis-charged after switching the patterns. ### Claim 6 (depends on 1) The inference operation method according to claim 1, wherein in the string selecting line group pioneering scheme, the string selecting line groups are switched before any one of the word lines is switched. ### Claim 7 (depends on 1) The inference operation method according to claim 1, wherein in the string selecting line group pioneering scheme, when the string selecting line groups are switched, voltages of the word lines are held. ### Claim 8 (depends on 1) The inference operation method according to claim 1, wherein in the string selecting line group pioneering scheme, one of the word lines is pre-charged before switching the string selecting line groups, and dis-charged after switching the string selecting line groups. ### Claim 9 (depends on 1) The inference operation method according to claim 1, wherein in the string selecting line group pioneering scheme, when one of the word lines is switched, any one of the string selecting line groups is not switched. ### Claim 10 A controlling circuit of a 3D NAND artificial intelligence accelerator, wherein the 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line, a plurality of filter data bits are stored in the memory cells that are selected by the word lines, the string selecting lines and the bit lines when being read, a plurality of patterns are inputted to the bit lines for performing a Multiply-Accumulation (MAC) operation, and the controlling circuit comprising: a bit line controller, configured to input the patterns to the bit lines; and a word line and string selecting line controller, configured to switch the word lines to switch the filter data bits, and configured to switch the string selecting line groups to switch the filter data bits; wherein in a word line pioneering scheme and a string selecting line group pioneering scheme, when the bit line controller switches the patterns inputted to each of the bit lines, any one of the word lines is not switched and any one of the string selecting line groups is not switched; wherein in the word line pioneering scheme and the string selecting line group pioneering scheme, when the patterns are switched, voltages of the word lines are held; and when the patterns are switched, voltages of the string selecting lines are held. ### Claim 11 (depends on 10) The controlling circuit according to claim 10, wherein in the word line pioneering scheme and the string selecting line group pioneering scheme, one of the word lines is pre-charged before switching the patterns, and dis-charged after switching the patterns. ### Claim 12 (depends on 10) The controlling circuit according to claim 10, wherein in the word line pioneering scheme, the word lines are switched before any one of the string selecting line groups is switched; and when the word lines are switched, voltages of the string selecting lines are held. ### Claim 13 (depends on 10) The controlling circuit according to claim 10, wherein in the word line pioneering scheme, one of the string selecting line groups is pre-charged before switching the word lines, and dis-charged after switching the word lines; and when one of the string selecting line groups is switched, any one of the word lines is not switched. ### Claim 14 (depends on 10) The controlling circuit according to claim 10, wherein in the string selecting line group pioneering scheme, one of the string selecting line groups is pre-charged before switching the patterns, and dis-charged after switching the patterns. ### Claim 15 (depends on 10) The controlling circuit according to claim 10, wherein in the string selecting line group pioneering scheme, the string selecting line groups are switched before any one of the word lines is switched. ### Claim 16 (depends on 10) The controlling circuit according to claim 10, wherein in the string selecting line group pioneering scheme, when the string selecting line groups are switched, voltages of the word lines are held. ### Claim 17 (depends on 10) The controlling circuit according to claim 10, wherein in the string selecting line group pioneering scheme, one of the word lines is pre-charged before switching the string selecting line groups, and dis-charged after switching the string selecting line groups. ### Claim 18 (depends on 10) The controlling circuit according to claim 10, wherein in the string selecting line group pioneering scheme, when one of the word lines is switched, any one of the string selecting line groups is not switched.