# US 11,309,024 B2 · Memory cell programming that cancels threshold voltage drift > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,024 B2 - Document ID: US11309024B2 - Status: Granted - Kind: B2 - Application number: 17/005,739 - Filed: 2020-08-28 - Published: 2022-03-03 - Granted: 2022-04-19 - Earliest claimed: 2020-08-28 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Hari Giduturi - Web page: https://patentgrep.com/patent/US11309024B2 ## CPC - G11C 13/0069: {Writing or programming circuits or methods} - G11C 13/003: {Cell access} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 2013/0073: {Write using bi-directional cell biasing} - G11C 2013/0078: {Write using current through the cell} - G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse} - G11C 2213/15: Current-voltage curve - G11C 2213/73: Array where access device function, e.g. diode function, being merged with memorizing function of memory element - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude. ## Claims ### Claim 1 An apparatus, comprising: a memory having a plurality of memory cells; and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by: applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude; and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude; wherein the circuitry is configured to program the memory cell to the one of the two possible data states without determining whether the memory cell snaps back in response to either the first applied voltage pulse or the second applied voltage pulse. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first polarity is opposite a polarity direction of the one of the two possible data states to which the memory cell is being programmed. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein each of the plurality of memory cells is a self-selecting memory cell in which a single material serves as a select element and a storage element. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the single material is a chalcogenide material. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the memory includes a plurality of access lines coupled to the plurality of memory cells; the memory cell being programmed is coupled to one of the plurality of access lines; and the circuitry is configured to program the memory cell to the one of the two possible data states without applying a voltage to the plurality of access lines to which the memory cell being programmed is not coupled. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the circuitry is configured to program the memory cell to the one of the two possible data states by turning off a current to the memory cell after applying the first voltage pulse to the memory cell and before applying the second voltage pulse to the memory cell. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the second magnitude is greater than the first magnitude. ### Claim 8 A method of operating memory, comprising: programming a memory cell to one of two possible data states by: applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude; applying a second voltage pulse to the memory cell, wherein: the second voltage pulse has a second polarity that is opposite the first polarity and is a polarity direction of the one of the two possible data states to which the memory cell is being programmed; and the second voltage pulse has a second magnitude; and applying a current pulse to the memory cell while the second voltage pulse is being applied to the memory cell. ### Claim 9 (depends on 8) The method of claim 8, wherein the first polarity is a positive polarity. ### Claim 10 (depends on 8) The method of claim 8, wherein the first polarity is a negative polarity. ### Claim 11 (depends on 8) The method of claim 8, wherein applying the first voltage pulse to the memory cell adjusts a threshold voltage of the memory cell to a threshold voltage to which the memory cell was previously programmed. ### Claim 12 (depends on 8) The method of claim 8, wherein the current pulse has a negative polarity. ### Claim 13 (depends on 8) The method of claim 8, wherein the current pulse has a positive polarity. ### Claim 14 An apparatus, comprising: a memory having a plurality of memory cells; and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by: applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a positive polarity and a first magnitude, wherein the first magnitude is a same magnitude as a voltage used to distinguish memory cells of the plurality of memory cells programmed to the one of the two possible data states from memory cells of the plurality of memory cells programmed to the other one of the two possible data states; and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a negative polarity and a second magnitude. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the one of the two possible data states is a set data state. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the second magnitude is a maximum voltage magnitude used to program memory cells of the plurality of memory cells to the one of the two possible data states. ### Claim 17 A method of operating memory, comprising: programming a self-selecting memory cell to one of two possible data states by applying a voltage pulse to the self-selecting memory cell, wherein: the voltage pulse has a positive polarity and a magnitude that is less than a magnitude of a voltage used to distinguish self-selecting memory cells of the memory programmed to the one of the two possible data states from self-selecting memory cells of the memory programmed to the other one of the two possible data states; and the method comprises programming the self-selecting memory cell without determining whether the self-selecting memory cell snaps back in response to the applied voltage pulse. ### Claim 18 (depends on 17) The method of claim 17, wherein the one of the two possible data states is a reset data state. ### Claim 19 (depends on 17) The method of claim 17, wherein the method includes programming the self-selecting memory cell to the one of the two possible data states by applying an additional voltage pulse to the self-selecting memory cell before applying the voltage pulse to the self-selecting memory cell, wherein the additional voltage pulse has a negative polarity. ### Claim 20 (depends on 19) The method of claim 19, wherein the additional voltage pulse has a same magnitude as the voltage used to distinguish self-selecting memory cells of the memory programmed to the one of the two possible data states from self-selecting memory cells of the memory programmed to the other one of the two possible data states. ### Claim 21 (depends on 17) The method of claim 17, wherein the voltage pulse has a magnitude that is a maximum voltage magnitude used to program self-selecting memory cells of the memory to the one of the two possible data states. ### Claim 22 An apparatus, comprising: a memory having a plurality of memory cells; and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by: applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a negative polarity and a first magnitude; and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a positive polarity and a second magnitude; wherein: the memory includes a plurality of access lines coupled to the plurality of memory cells; the memory cell being programmed is coupled to one of the plurality of access lines; and the circuitry is configured to program the memory cell to the one of the two possible data states without applying a voltage to the plurality of access lines to which the memory cell being programmed is not coupled.