# US 11,309,023 B1 · Memory cycling tracking for threshold voltage variation systems and methods

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- Number: US 11,309,023 B1
- Document ID: US11309023B1
- Status: Granted
- Kind: B1
- Application number: 17/091,860
- Filed: 2020-11-06
- Granted: 2022-04-19
- Earliest claimed: 2020-11-06
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Hari Giduturi
- Web page: https://patentgrep.com/patent/US11309023B1

## CPC

- G11C 13/003: {Cell access}
- G06F 9/30116: {Shadow registers, e.g. coupled registers, not forming part of the register space}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]}
- G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles}
- G11C 13/0038: {Power supply circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2213/71: Three dimensional array
- G11C 2213/72: Array wherein the access device being a diode
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory system may include multiple memory cells to store logical data and cycle tracking circuitry to track a number of cycles associated the memory cells. The cycles may be representative of one or more past accesses of the memory cells. The memory system may also include control circuitry to access the memory cells. Accessing of the memory cell may include a read operation, a write operation, or both. During the accessing of the memory cell, the control circuitry may determine a voltage parameter of the access based at least in part on the tracked number of cycles.

## Claims

### Claim 1

A system comprising:
a plurality of memory cells configured to store logical data;
cycle tracking circuitry configured to track a number of cycles associated with a memory cell of the plurality of memory cells, wherein the cycles are representative of one or more past accesses of the memory cell; and
control circuitry configured to access the memory cell, wherein the access of the memory cell comprises a read operation of the memory cell, a write operation to the memory cell, or both, wherein the control circuitry is configured to determine a voltage parameter of the access of the memory cell based at least in part on the tracked number of cycles of the memory cell.

### Claim 2 (depends on 1)

The system of claim 1, wherein the plurality of memory cells comprises a plurality of chalcogenide memory cells.

### Claim 3 (depends on 1)

The system of claim 1, wherein the cycle tracking circuitry comprises:
a cycle count register configured to store a cycle count value representative of the tracked number of cycles of the memory cell; and
cycle count trigger circuitry configured to update the cycle count value of the cycle count register in response to the one or more past accesses of the memory cell and the access of the memory cell.

### Claim 4 (depends on 3)

The system of claim 3, wherein the cycle tracking circuitry is disposed on-die with the plurality of memory cells.

### Claim 5 (depends on 1)

The system of claim 1, wherein the cycle tracking circuitry comprises a plurality of shadow registers configured to define a plurality of memory blocks of the plurality of memory cells, wherein a memory block of the plurality of memory blocks comprises a set of consecutive memory addresses corresponding to a respective set of memory cells of the plurality of memory cells.

### Claim 6 (depends on 5)

The system of claim 5, wherein a shadow register of the plurality of shadow registers defines the memory block based at least in part on a start address stored in the shadow register and an end address stored in the shadow register.

### Claim 7 (depends on 6)

The system of claim 6, wherein the memory block comprises the memory cell, and wherein the cycle tracking circuitry comprises a cycle count register associated with the shadow register and configured to store a cycle count value representative of the tracked number of cycles of the memory cell, wherein, in response to a read request or a write request, the control circuitry is configured to reference the shadow register to access the cycle count value of the cycle count register.

### Claim 8 (depends on 1)

The system of claim 1, wherein the control circuitry is configured to determine a sense voltage for a read of the memory cell or a selection voltage of the memory cell based at least in part on the tracked number of cycles of the memory cell.

### Claim 9 (depends on 1)

The system of claim 1, wherein the control circuitry is configured to determine a program current of the memory cell based at least in part on the tracked number of cycles of the memory cell.

### Claim 10

A memory device comprising:
a memory array comprising a plurality of memory addresses associated with a plurality of memory cells;
a plurality of shadow registers configured to define a plurality of memory blocks of the memory array, wherein each memory block of the plurality of memory blocks comprises a subset of memory addresses of the plurality of memory addresses; and
a plurality of cycle count registers, wherein a cycle count register of the plurality of cycle count registers corresponds to a shadow register of the plurality of shadow registers, wherein the shadow register is configured to define a memory block of the plurality of memory blocks, wherein the cycle count register is configured to maintain a cycle count value corresponding to a number of previous operations performed on a memory cell of the memory block.

### Claim 11 (depends on 10)

The memory device of claim 10, comprising control circuitry configured to, in response to a request to access the memory cell, determine a voltage parameter of the access of the memory cell based at least in part on the cycle count value of the cycle count register.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the voltage parameter comprises a sense voltage of a read operation or a pre-read operation of the access of the memory cell.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the voltage parameter comprises a selection voltage of the access of the memory cell.

### Claim 14 (depends on 11)

The memory device of claim 11, comprising shift index circuitry configured to convert the cycle count value into a shift index, wherein conversion of the cycle count value into the shift index comprises determining into which of a plurality of windows the cycle count value falls, wherein each window of the plurality of windows is associated with a respective shift index, and wherein the control circuitry is configured to determine the voltage parameter based at least in part on the respective shift index corresponding to a window of the plurality of windows that the cycle count value falls.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the voltage parameter comprises a read sense voltage, and wherein the respective shift index of each window of the plurality of windows corresponds to a different read sense voltage.

### Claim 16 (depends on 11)

The memory device of claim 11, wherein the previous operations comprise read operations and write operations.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein a write operation of the write operations corresponds to a larger increase of the cycle count value than a read operation of the read operations.

### Claim 18 (depends on 16)

The memory device of claim 16, comprising a cycle count trigger configured to update the cycle count value of the cycle count register in response to a new operation, wherein the new operation comprises a read of the memory cell or a write to the memory cell.

### Claim 19

A method comprising:
receiving a write request;
in response to receiving the write request, writing data to a plurality of memory cells of a memory device;
assigning the plurality of memory cells to a memory block;
tracking a cycle count value of the memory block, wherein the cycle count value comprises an indication of a number of operations performed on the plurality of memory cells of the memory block; and
accessing a memory cell of the memory block, wherein accessing the memory block comprises:
determining a selection voltage of the memory cell based at least in part on the cycle count value;
determining a read sense voltage of the memory cell based at least in part on the cycle count value; or
both.

### Claim 20 (depends on 19)

The method of claim 19, wherein tracking the cycle count value of the memory block comprises:
storing the cycle count value in a cycle count register; and
updating the cycle count register in response to an operation being performed on the memory cell.

### Claim 21 (depends on 20)

The method of claim 20, wherein updating the cycle count register comprises:
in response to determining that the operation comprises a read operation, updating the cycle count value with a first increment; and
in response to determining that the operation comprises a write operation, updating the cycle count value with a second increment, wherein the second increment is greater than the first increment.

### Claim 22 (depends on 19)

The method of claim 19, wherein assigning the plurality of memory cells to the memory block comprises:
storing a start address of the plurality of memory cells in a shadow register;
storing an end address of the plurality of memory cells in the shadow register; or
both.

### Claim 23 (depends on 22)

The method of claim 22, wherein the shadow register is associated with a cycle count register configured to store the cycle count value.

### Claim 24 (depends on 19)

The method of claim 19, wherein accessing the memory cell comprises:
matching a memory address of the memory cell to the memory block; and
in response to matching the memory address to the memory block, referencing a cycle count register associated with the memory block to obtain the cycle count value.