# US 11,309,021 B2 · Systems and methods for stabilizing cell threshold voltage

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- Number: US 11,309,021 B2
- Document ID: US11309021B2
- Status: Granted
- Kind: B2
- Application number: 16/760,420
- Filed: 2019-12-03
- Published: 2021-12-30
- Granted: 2022-04-19
- Earliest claimed: 2019-12-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Paolo Amato; Marco Sforzin
- Web page: https://patentgrep.com/patent/US11309021B2

## CPC

- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2013/0073: {Write using bi-directional cell biasing}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C 2213/73: Array where access device function, e.g. diode function, being merged with memorizing function of memory element
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.

## Claims

### Claim 1

A memory device comprising:
a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage; and
a logic circuit portion operatively coupled to the plurality of memory cells, wherein said logic circuit portion is configured to:
scan memory addresses of the memory device; and
generate seasoning pulses to be applied to addressed pages of the memory device for stabilization of the threshold voltage of the memory cells.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the logic circuit portion comprises a counter configured to scan the memory addresses of the memory device, said counter being operatively coupled with a manging unit of the memory device for application of said seasoning pulses to the addressed pages.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the logic circuit portion is configured so that a sequence comprising a pre-set number of seasoning pulses is applied to the memory cells.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the logic circuit portion comprises a further counter adapted to count the number of applied seasoning pulses, and wherein said logic circuit portion is further configured to compare the counted pulses with the pre-set number.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the logic circuit portion is configured to generate seasoning pulses having a longer duration than programming pulses for said memory cells.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the logic circuit portion is configured to apply a pre-set number of seasoning pulses to a selected first portion of the addressed pages of the memory device in a first seasoning process, and then to apply the pre-set number of seasoning pulses to a selected second portion of addressed pages of the memory device in a second seasoning process.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the logic circuit portion is configured to apply a first number of seasoning pulses to all the addressed pages of the memory device in a first seasoning process, and then to apply subsequent seasoning pulses to all the addressed pages of the memory device in a second seasoning process.

### Claim 8 (depends on 1)

The memory device of claim 1, comprising a controller configured to generate access commands, said controller being coupled to the plurality of memory cells and configured to apply a reading voltage to memory cells during a reading operation to assess the logic state thereof.

### Claim 9 (depends on 8)

The memory device according to claim 8, wherein the logic circuit portion is embedded in the controller and is operatively coupled to a decoder of the memory device.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein a memory portion comprises a 3D cross point memory.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein the logic circuit portion is configured to scan the memory addresses and to generate the seasoning pulses in response to receiving a specific command or a specific sequence of signals applied to input/output pads of the device, and/or in response to receiving a specific supply voltage different from a nominal supply voltage.

### Claim 12 (depends on 1)

The memory device of claim 1, wherein said memory device is configured to be set in busy state during application of the seasoning pulses.

### Claim 13

An electronic system comprising:
a host device including a processor module;
a memory device operatively coupled to the host device; and
a managing unit of the memory device, wherein the memory device comprises:
a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage; and
a logic circuit portion operatively coupled to the plurality of memory cells, wherein said logic circuit portion is configured to:
scan memory addresses of the memory device; and
generate seasoning pulses to be applied to addressed pages of the memory device for stabilization of the threshold voltage of the memory cells.

### Claim 14 (depends on 13)

The electronic system of claim 13, wherein the logic circuit portion is configured to apply a pre-set number of seasoning pulses to a selected portion of the addressed pages of the memory device in foreground during operation of the processor, and then to apply the pre-set number of seasoning pulses to a selected second portion of addressed pages of the memory device in background during operation of the processor.

### Claim 15 (depends on 14)

The electronic system of claim 14, wherein the host is a mobile phone, and wherein the selected portion of the memory device comprises a portion of Source Measurement Unit (SMU) and a portion of Line Monitor Unit (LMU).

### Claim 16 (depends on 13)

The electronic system of claim 13, wherein the logic circuit portion is configured to apply a first number of the seasoning pulses to all the addressed pages of the memory device in foreground during operation of the processor, and then to apply subsequent seasoning pulses to all the addressed pages of the memory device in background during operation of the processor.

### Claim 17 (depends on 13)

The electronic system of claim 13, comprising a counter configured to scan the memory addresses of the memory device, said counter being operatively coupled with the manging unit of the memory device for application of said seasoning pulses to the addressed pages.

### Claim 18 (depends on 13)

The electronic system of claim 13, comprising a controller configured to generate access commands, said controller being in operative connection with the processor module.

### Claim 19 (depends on 13)

The electronic system of claim 13, wherein the managing unit of the logic circuit portion is in operative connection with a seasoning pulse generation unit for generation and application of said seasoning pulses to the memory cells of the memory device.

### Claim 20 (depends on 13)

The electronic system of claim 13, wherein the logic circuit portion is configured to scan the memory addresses and to generate the seasoning pulses upon receiving a specific command or a specific sequence of signals applied to input/output pads of the system, and/or upon receiving a specific supply voltage different from a nominal supply voltage.

### Claim 21 (depends on 13)

The electronic system of claim 13, further comprising a communication module configured to enable communications with other electronic systems, and/or interface devices configured to enable interface of a user.

### Claim 22

A method for stabilizing threshold voltages of a plurality of memory cells included in a memory device, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, the method comprising the steps of:
scanning memory addresses of the memory device, wherein said scanning is performed by a logic circuit portion internal to the memory device;
generating, inside the logic circuit portion of the memory device, a seasoning pulse to be applied to addressed pages of the memory device; and
applying a sequence of seasoning pulses to said addressed pages of the memory device.

### Claim 23 (depends on 22)

The method of claim 22, wherein applying the sequence of seasoning pulses comprises applying a pre-set number of seasoning pulses that corresponds to a number required to stabilize the threshold voltages, the method further comprising a step of comparing the actual number of applied pulses to said pre-set number of seasoning pulses.

### Claim 24 (depends on 22)

The method of claim 22, wherein applying a sequence of seasoning pulses involves applying a pulse of longer pulse duration than programming pulses used to program said cell.

### Claim 25 (depends on 22)

The method of claim 22, wherein, during application of the seasoning pulses, a busy state is set and no other operation is performed.

### Claim 26 (depends on 22)

The method of claim 22, comprising a first step of applying the sequence of seasoning pulses to a selected portion of the addressed pages in a first seasoning process, and then a second step of applying the sequence of seasoning pulses to a second selected portion of the addressed pages in a second seasoning process.

### Claim 27 (depends on 22)

The method of claim 22, comprising a first step of applying a first number of the seasoning pulses to all the addressed pages in a first seasoning process, and then a second step of applying subsequent seasoning pulses to all the addressed pages in a second seasoning process.

### Claim 28 (depends on 22)

The method of claim 22, wherein said steps are executed upon receiving a specific command or a specific sequence of signals, and/or upon receiving a specific supply voltage different from a nominal supply voltage.

### Claim 29 (depends on 22)

A method for operating a memory device, comprising the steps of:
performing a first seasoning process at wafer level;
performing a second seasoning process at unit level after assembly and bonding of the memory device; and
performing a third seasoning process at unit level after soldering the memory device, wherein at least one of the seasoning processes are performed autonomously according to claim 22.