# US 11,309,019 B2 · Semiconductor memory device which stores plural data in a cell

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- Number: US 11,309,019 B2
- Document ID: US11309019B2
- Status: Granted
- Kind: B2
- Application number: 17/101,431
- Filed: 2020-11-23
- Published: 2021-04-08
- Granted: 2022-04-19
- Earliest claimed: 2004-01-30
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Noboru Shibata; Tomoharu Tanaka
- Web page: https://patentgrep.com/patent/US11309019B2

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- G11C 16/12: Programming voltage switching circuits
- G11C 16/3454: {Arrangements for verifying correct programming or for detecting overprogrammed cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 2211/5621: Multilevel programming verification
- G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

## Claims

### Claim 1

A method for controlling a semiconductor memory device, the semiconductor memory device including: a memory cell array including a plurality of memory cells arranged in a matrix, each of the memory cells being capable of storing data by n levels; and a control circuit configured to control the memory cell array, the method comprising:
writing first data by m levels (m<n) to a first memory cell;
subsequently writing second data by the m levels (m<n) to a second memory cell adjacent to the first memory cell; and
subsequently writing, to the first memory cell, third data by the n levels formed of the first data by the m levels stored in the first memory cell and fourth data by an (n-m) level.

### Claim 2 (depends on 1)

The method for controlling the semiconductor memory device according to claim 1, further comprising:
writing, after the second data by the m levels is written to the second memory cell, fifth data by the m levels to a third memory cell adjacent to the second memory cell; and
subsequently writing, to the second memory cell, sixth data by the n levels formed of the second data by the m levels stored in the second memory cell and seventh data by the (n-m) level.

### Claim 3 (depends on 1)

The method for controlling the semiconductor memory device according to claim 1, wherein the semiconductor memory device further includes:
a first word line connected to the first memory cell; and
a second word line connected to the second memory cell,
wherein the first word line and the second word line are adjacent to each other.

### Claim 4 (depends on 2)

The method for controlling the semiconductor memory device according to claim 2, wherein the semiconductor memory device further includes:
a first word line connected to the first memory cell;
a second word line connected to the second memory cell; and
a third word line connected to the third memory cell,
wherein the first word line and the second word line are adjacent to each other, and
the second word line and the third word line are adjacent to each other.

### Claim 5 (depends on 1)

The method for controlling the semiconductor memory device according to claim 1, wherein the memory cells constitute a NAND flash memory.

### Claim 6 (depends on 2)

The method for controlling the semiconductor memory device according to claim 2, wherein the third memory cell is adjacent to the second memory cell in a first row position different from a second row position of the first memory cell in the memory cell array.