# US 11,309,017 B2 · Memory systems and methods for improved power management

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- Number: US 11,309,017 B2
- Document ID: US11309017B2
- Status: Granted
- Kind: B2
- Application number: 17/100,850
- Filed: 2020-11-21
- Published: 2021-06-10
- Granted: 2022-04-19
- Earliest claimed: 2014-11-20
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; James E. Harris
- Web page: https://patentgrep.com/patent/US11309017B2

## CPC

- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

## Claims

### Claim 1

A memory module comprising:
memory devices each having a data interface, an address interface, an enable interface, and a chip-select interface; and
a command-buffer component coupled to the address interfaces, enable interfaces, and chip-select interfaces of the memory devices, the command-buffer component to receive memory commands, memory addresses associated with the memory commands, and encoded chip-select information associated with the memory commands, the command-buffer component decoding the chip-select information, responsively issuing an enable signal to a subset of the enable interfaces to enable a corresponding subset of the memory devices, and issuing chip-select signals to ones of the enabled subset of the memory devices.

### Claim 2 (depends on 1)

The memory module of claim 1, wherein the command-buffer component divides the memory devices into sub-ranks of memory devices, the number of memory devices in each of the sub-ranks of the memory devices a function of a configuration value.

### Claim 3 (depends on 2)

The memory module of claim 2, wherein the memory module is one of multiple memory modules in a memory system, and wherein the configuration value indicates the number of the memory modules in the memory system.

### Claim 4 (depends on 2)

The memory module of claim 2, wherein the memory module is one of multiple memory modules in a memory system, and each of the memory modules enabling one of the sub-ranks of the memory devices.

### Claim 5 (depends on 1)

The memory module of claim 1, wherein the command-buffer component decodes the chip-select information to issue the enable signals and second chip-select information to issue the chip-select signals to ones of the enabled subset of the memory devices.

### Claim 6 (depends on 5)

The memory module of claim 5, the command-buffer component including a register to store the decoded chip-select information pending receipt of the second chip-select information.

### Claim 7 (depends on 1)

The memory module of claim 1, further comprising a data-buffer component coupled to at least one of the memory devices, the command-buffer component to issue a data-buffer enable signal to the data-buffer component responsive to the decoded chip-select information.

### Claim 8

A method for providing access to a rank of memory devices on at least one memory module, the rank including a first sub-rank of memory devices and a second sub-rank of memory devices, the method comprising:
receiving an enable command at the at least one memory module, the enable command accompanying chip-select information;
powering the memory devices in the first and second sub-ranks of the memory devices responsive to the chip-select information; and
asserting chip-select signals to the powered memory devices in the first and second sub-ranks of the memory devices responsive to the chip-select information.

### Claim 9 (depends on 8)

The method of claim 8, wherein the rank of memory devices are a set of memory devices accessed simultaneously, and each of the first and second sub-ranks is a module-specific fraction of the rank.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
storing the chip-select information accompanying the enable command;
receiving a second command with the chip-select information;
powering the memory devices in the first and second sub-ranks of the memory devices responsive to the stored chip-select information; and
asserting the chip-select signals responsive to the second command.

### Claim 11 (depends on 8)

The method of claim 8, wherein powering the memory devices comprises commanding the memory devices to exit a low-power mode.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
receiving an activate command at the at least one memory module; and
activating the first and second sub-ranks of the memory devices responsive to the activate command.

### Claim 13 (depends on 8)

The method of claim 8, the memory module further including data buffers to communicate data with the memory devices, the method further comprising powering a subset of the data buffers responsive to the chip-select information.

### Claim 14

A memory module comprising:
a number of memory devices each having a memory-device enable terminal;
a command port to receive commands from a controller component external to the memory module; and
a decoder communicatively coupled to the command port and the memory-device enable terminals, the decoder to:
receive a configuration value from the controller component specifying a fraction of the number of the memory devices;
receive, as one of the commands, an enable command accompanying chip-select information;
decode the chip-select information responsive to the configuration value specifying the fraction of the number of the memory devices, the decoding specifying a subset of the memory devices, the subset of the memory devices of the fraction of the number of the memory devices; and
power the specified subset of the memory devices responsive to the decoded chip-select information.

### Claim 15 (depends on 14)

The memory module of claim 14, wherein the decoder is instantiated on a command-buffer component on the memory module.

### Claim 16 (depends on 15)

The memory module of claim 15, further comprising data-buffer components coupled to the memory devices to communicate data between the memory devices and the controller component.

### Claim 17 (depends on 16)

The memory module of claim 16, wherein the decoder directs the data-buffer components responsive to the configuration value.

### Claim 18 (depends on 17)

The memory module of claim 17, the decoder including a register to store the configuration value.

### Claim 19 (depends on 17)

The memory module of claim 17, the decoder including a register to store a value specifying the subset of the memory devices.

### Claim 20 (depends on 17)

The memory module of claim 17, the decoder including a register to store the decoded chip-select information.