# US 11,309,015 B2 · Floating body DRAM with reduced access energy

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,309,015 B2
- Document ID: US11309015B2
- Status: Granted
- Kind: B2
- Application number: 16/999,869
- Filed: 2020-08-21
- Published: 2021-02-04
- Granted: 2022-04-19
- Earliest claimed: 2016-12-09
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; John Eric Linstadt; Zhichao Lu; Kenneth Lee Wright
- Web page: https://patentgrep.com/patent/US11309015B2

## CPC

- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 2207/2263: Write conditionally, e.g. only if new data and old data differ
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

## Claims

### Claim 1

A memory controller, comprising: a transfer interface to transmit a read command to access first read data stored in a first group of floating body storage cells; conditional writeback circuitry coupled to the transfer interface, the conditional writeback circuitry to generate a writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a first sense characteristic; and wherein the transfer interface is configured to conditionally perform a writeback operation of sensed data associated with the read command in response to the writeback command generated by the conditional writeback circuitry.

### Claim 2 (depends on 1)

The memory controller of claim 1: wherein the conditional writeback circuitry generates the writeback command randomly based on the predetermined probability.

### Claim 3 (depends on 2)

The memory controller of claim 2, wherein the conditional writeback circuitry further comprises: a control register to store a value N corresponding to the predetermined probability.

### Claim 4 (depends on 3)

The memory controller of claim 3, wherein the conditional writeback circuitry further comprises: a random signal generator configured to generate the writeback command with the predetermined probability based on the relationship 1/N.

### Claim 5 (depends on 1)

The memory controller of claim 1, wherein the conditional writeback circuitry further comprises: circuitry to generate the threshold count of the number of accesses to the storage cells, the threshold count stored as a tag.

### Claim 6 (depends on 5)

The memory controller of claim 5, wherein the conditional writeback circuitry further comprises: a control register to store a value M corresponding to the threshold count; and wherein the conditional writeback circuitry generates the writeback command when the threshold count is reached or exceeded.

### Claim 7 (depends on 1)

The memory controller of claim 1, further comprising: circuitry to generate a parity count for read data accessed from the first group of the storage cells; and wherein the conditional writeback circuitry selectively generates the writeback command based on the parity count.

### Claim 8 (depends on 7)

The memory controller of claim 7, further comprising: a control register to store a parity value corresponding to data written to the first group of the storage cells; and wherein the conditional writeback circuitry selectively generates the writeback command when the parity count differs from the parity value.

### Claim 9 (depends on 1)

The memory controller of claim 1, wherein the conditional writeback circuitry further comprises: circuitry to compare the tag value to a reference value; and wherein the conditional writeback circuitry selectively generates the writeback command based on the comparison.

### Claim 10 (depends on 1)

The memory controller of claim 1, wherein: the transfer interface and the conditional writeback circuitry are configured to operate at cryogenic temperature.

### Claim 11

A method of operation in an integrated circuit (IC) memory controller, the method comprising:
transmitting read transaction component signals for accessing a first group of floating body dynamic random access memory (FBDRAM) storage cells, the read transaction component signals including an activate command and a read command;
conditionally generating a writeback command with conditional writeback circuitry, the conditional writeback circuitry generating the writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a first sense characteristic; and
performing a writeback operation of sensed data associated with the read command in response to the writeback command.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
conditionally generating the writeback command is carried out randomly based on the predetermined probability.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
retrieving a value N from a control register, the value N corresponding to the predetermined probability; and
generating the writeback command with a random signal generator based on the relationship 1/N.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
generating the threshold count of the number of accesses to the first group of the FBDRAM storage cells, the threshold count stored as a tag; and
wherein the conditional writeback circuitry conditionally generates the writeback command based on the threshold count.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
retrieving a predetermined threshold value from a control register;
comparing the threshold count to the predetermined threshold value; and
generating the writeback command based on whether the threshold count meets or exceeds the predetermined threshold value.

### Claim 16 (depends on 11)

The method of claim 11, wherein data written to the first group of the FBDRAM storage cells exhibits a second sense characteristic, and wherein a second group of the FBDRAM storage cells stores a tag value that is accessed each time a read operation for the data in the first group of the FBDRAM storage cells takes place, the tag value exhibiting the first sense characteristic that is less than the second sense characteristic, further comprising:
retrieving the tag value from the second group of the FBDRAM storage cells;
comparing the tag value to a reference value; and
generating the writeback command based on the comparing.

### Claim 17 (depends on 11)

The method of claim 11, further comprising:
operating the IC memory controller at cryogenic temperature.

### Claim 18

A memory comprising:
a memory device including storage cells, each storage cell formed with a metal-oxide-semiconductor (MOS) transistor having a floating body, wherein data is stored as charge in the floating body;
memory control circuitry to issue a read command to the memory device, the memory control circuitry including a transfer interface to receive a read command to access first data stored in a first group of the storage cells; and
wherein the transfer interface conditionally performs a writeback operation associated with the read command in response to a writeback command generated by conditional writeback circuitry disposed in the memory control circuitry, the conditional writeback circuitry generating the writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a sense characteristic.

### Claim 19 (depends on 18)

The memory of claim 18, wherein the memory control circuitry further comprises:
a control register to store at least one of a value N corresponding to the predetermined probability, the threshold count of the number of accesses to the first group of the storage cells, and a parity value corresponding to data written to the first group of the storage cells.

### Claim 20 (depends on 18)

The memory of claim 18, configured to operate at cryogenic temperature.