# US 11,309,013 B2 · Memory device for reducing resources used for training

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- Number: US 11,309,013 B2
- Document ID: US11309013B2
- Status: Granted
- Kind: B2
- Application number: 17/130,493
- Filed: 2020-12-22
- Published: 2021-11-04
- Granted: 2022-04-19
- Earliest claimed: 2020-04-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Byongmo Moon; Beomyong Kil; Jihye Kim
- Web page: https://patentgrep.com/patent/US11309013B2

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/1093: {Input synchronization}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/409: Read-write [R-W] circuits
- G11C 29/022: {in I/O circuitry}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/1066: {Output synchronization}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 2207/105: Aspects related to pads, pins or terminals
- G11C 2207/108: Wide data ports
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

## Claims

### Claim 1

A memory device comprising:
first power pins disposed in a first power area and configured to receive a first power voltage;
data pins configured to transmit or receive data signals, the data pins being disposed in a first region and a second region, the first region and the second region each including a portion of the first power area;
control pins configured to transmit or receive control signals, the control pins being disposed in the first region and the second region;
second power pins disposed in a second power area between the first region and the second region, the second power pins configured to receive a second power voltage different from the first power voltage; and
ground pins disposed in the second power area and configured to receive a ground voltage,
wherein the data pins and the control pins are divided into a plurality of pin groups, and
wherein a training value including transmission timing or receiving timing for each pin group of the plurality of pin groups is determined based on training at least one pin from each group of the plurality of pin groups.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein control pins of a first pin group from among the plurality of pin groups comprise a pin configured to receive a write data strobe signal, and
control pins of a second pin group from among the plurality of pin groups do not comprise the pin configured to receive the write data strobe signal.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the memory device is configured to sample the data signals and the control signals based on the write data strobe signal.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the memory device is configured to transmit the data signals and the control signals based on the write data strobe signal.

### Claim 5 (depends on 2)

The memory device of claim 2, further comprising:
a plurality of repeater circuitries configured to transmit the write data strobe signal to a region in which the second pin group is located.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein from among the plurality of repeater circuitries, a first repeater circuitry and a second repeater circuitry are arranged to be symmetrical with respect to the first power area.

### Claim 7 (depends on 2)

The memory device of claim 2, wherein the control pins of the second pin group comprise a pin configured to transmit or to receive at least one of an error correction code signal, a data parity signal, a data bus inversion signal, an error severity signal, and a data error signal.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein the first power voltage is less than the second power voltage.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein pins of each of the plurality of pin groups are arranged to be symmetrical with respect to the first power area.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein each of the plurality of pin groups comprises at least eight pins.

### Claim 11

A memory device comprising:
a first pin group including a first data pin configured to transmit or receive a first data signal and a first control pin configured to transmit or receive a first control signal;
a second pin group including a second data pin configured to transmit or receive a second data signal and a second control pin configured to transmit or receive a second control signal;
a third control pin configured to receive a write data strobe signal;
first power pins configured to receive a first power voltage, the first power pins being located in a first power area positioned in each of a first region in which the first pin group is located and a second region in which the second pin group is located;
second power pins configured to receive a second power voltage different from the first power voltage, the second power pins being located in a second power area positioned between the first region and the second region;
ground pins configured to receive a ground voltage, the ground pins being located in the second power area; and
a write data strobe tree circuitry configured to transmit a first internal write data strobe signal with a first toggle timing to a first circuit block corresponding to the first pin group and to transmit a second internal write data strobe signal with a second toggle timing to a second circuit block corresponding to the second pin group, based on the write data strobe signal,
wherein the first toggle timing is different from the second toggle timing.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein pins of the first pin group and pins of the second pin group are arranged to be symmetrical with respect to the second power area.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein a first training value including transmission timing or receiving timing of the first pin group is determined based on training one of the first data pin and the first control pin, and a second training value including transmission timing or receiving timing of the second pin group is determined based on training one of the second data pin and the second control pin.

### Claim 14 (depends on 11)

The memory device of claim 11, wherein the first circuit block configured to receive the first data signal and the first control signal transmitted through the first pin group and to sample the first data signal and the first control signal based on the first internal write data strobe signal, and
the second circuit block configured to receive the second data signal and the second control signal transmitted through the second pin group and to sample the second data signal and the second control signal based on the second internal write data strobe signal.

### Claim 15 (depends on 11)

The memory device of claim 11, wherein the write data strobe tree circuitry includes first repeater circuitries on the first region and second repeater circuitries on the second region, and the first repeater circuitries and the second repeater circuitries are arranged symmetrical with respect to the second power area.

### Claim 16 (depends on 11)

The memory device of claim 11, wherein a layout of circuits on the first region is the same as a layout of circuits on the second region.

### Claim 17

A memory device comprising:
a write data strobe pin configured to receive a write data strobe signal;
a first pin group configured to receive first data signals sampled based on the write data strobe signal; and
a second pin group configured to receive second data signals sampled based on the write data strobe signal,
wherein a first training value of the first pin group is determined based on training a first pin of the first pin group, and
a second training value of the second pin group of pins is determined based on training a second pin of the second pin group.

### Claim 18 (depends on 17)

The memory device of claim 17, further comprising:
a first receiver group configured to receive the first data signals transmitted through the first pin group;
a second receiver group configured to receive the second data signals transmitted through the second pin group; and
a write data strobe tree circuitry configured to transmit a first internal write data strobe signal to the first receiver group through repeater circuitries on a first path and to transmit a second internal write data strobe signal to the second receiver group through repeater circuitries on a second path, based on the write data strobe signal transmitted through the write data strobe pin,
wherein the first receiver group is configured to sample the first data signals based on toggle timing of the first internal write data strobe signal, and
the second receiver group is configured to sample the second data signals based on toggle timing of the second internal write data strobe signal.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein receivers of the first receiver group are arranged at the same distance from a repeater circuitry of the repeater circuitries located last on the first path.

### Claim 20 (depends on 18)

The memory device of claim 18, wherein lengths of signal lines that transmit the first data signals from the first group of pins to the first receiver group are the same.